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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liu49912402014-11-24 17:11:56 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Rajesh Bhagataec38012021-11-09 16:30:38 +05304 * Copyright 2020-2021 NXP
Shengzhou Liu49912402014-11-24 17:11:56 +08005 */
6
7/*
8 * T1024/T1023 RDB board configuration file
9 */
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
Simon Glassfb64e362020-05-10 11:40:09 -060014#include <linux/stringify.h>
15
Shengzhou Liu49912402014-11-24 17:11:56 +080016/* High Level Configuration Options */
Shengzhou Liu49912402014-11-24 17:11:56 +080017#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liu49912402014-11-24 17:11:56 +080018#define CONFIG_ENABLE_36BIT_PHYS
19
Shengzhou Liu49912402014-11-24 17:11:56 +080020#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080021#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Shengzhou Liu49912402014-11-24 17:11:56 +080022
Shengzhou Liu49912402014-11-24 17:11:56 +080023#ifdef CONFIG_RAMBOOT_PBL
Shengzhou Liu49912402014-11-24 17:11:56 +080024#define RESET_VECTOR_OFFSET 0x27FFC
25#define BOOT_PAGE_OFFSET 0x27000
Shengzhou Liu49912402014-11-24 17:11:56 +080026
Miquel Raynald0935362019-10-03 19:50:03 +020027#ifdef CONFIG_MTD_RAW_NAND
Shengzhou Liu49912402014-11-24 17:11:56 +080028#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080029#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
30#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Pali Rohár7e814162022-04-25 14:21:20 +053031#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
32#define CONFIG_SYS_MPC85XX_NO_RESETVEC
33#endif
Shengzhou Liu49912402014-11-24 17:11:56 +080034#endif
35
36#ifdef CONFIG_SPIFLASH
tang yuantian8dc02f32014-12-17 15:42:54 +080037#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu49912402014-11-24 17:11:56 +080038#define CONFIG_SPL_SPI_FLASH_MINIMAL
39#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080040#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
41#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Shengzhou Liu49912402014-11-24 17:11:56 +080042#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
Shengzhou Liu49912402014-11-24 17:11:56 +080043#ifndef CONFIG_SPL_BUILD
44#define CONFIG_SYS_MPC85XX_NO_RESETVEC
45#endif
Shengzhou Liu49912402014-11-24 17:11:56 +080046#endif
47
48#ifdef CONFIG_SDCARD
tang yuantian8dc02f32014-12-17 15:42:54 +080049#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu49912402014-11-24 17:11:56 +080050#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
tang yuantian8dc02f32014-12-17 15:42:54 +080051#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
52#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Shengzhou Liu49912402014-11-24 17:11:56 +080053#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
Shengzhou Liu49912402014-11-24 17:11:56 +080054#ifndef CONFIG_SPL_BUILD
55#define CONFIG_SYS_MPC85XX_NO_RESETVEC
56#endif
Shengzhou Liu49912402014-11-24 17:11:56 +080057#endif
58
59#endif /* CONFIG_RAMBOOT_PBL */
60
Shengzhou Liu49912402014-11-24 17:11:56 +080061#ifndef CONFIG_RESET_VECTOR_ADDRESS
62#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63#endif
64
Shengzhou Liu49912402014-11-24 17:11:56 +080065/* PCIe Boot - Master */
66#define CONFIG_SRIO_PCIE_BOOT_MASTER
67/*
68 * for slave u-boot IMAGE instored in master memory space,
69 * PHYS must be aligned based on the SIZE
70 */
71#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
72#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
73#ifdef CONFIG_PHYS_64BIT
74#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
75#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
76#else
77#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
78#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
79#endif
80/*
81 * for slave UCODE and ENV instored in master memory space,
82 * PHYS must be aligned based on the SIZE
83 */
84#ifdef CONFIG_PHYS_64BIT
85#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
86#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
87#else
88#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
89#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
90#endif
91#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
92/* slave core release by master*/
93#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
94#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
95
96/* PCIe Boot - Slave */
97#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
98#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
99#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
100 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
101/* Set 1M boot space for PCIe boot */
102#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
103#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
104 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
105#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shengzhou Liu49912402014-11-24 17:11:56 +0800106#endif
107
Shengzhou Liu49912402014-11-24 17:11:56 +0800108/*
109 * These can be toggled for performance analysis, otherwise use default.
110 */
111#define CONFIG_SYS_CACHE_STASHING
Shengzhou Liu49912402014-11-24 17:11:56 +0800112#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
Shengzhou Liu49912402014-11-24 17:11:56 +0800113#ifdef CONFIG_DDR_ECC
Shengzhou Liu49912402014-11-24 17:11:56 +0800114#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
115#endif
116
Shengzhou Liu49912402014-11-24 17:11:56 +0800117/*
118 * Config the L3 Cache as L3 SRAM
119 */
120#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
121#define CONFIG_SYS_L3_SIZE (256 << 10)
122#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
Tom Rini5cd7ece2019-11-18 20:02:10 -0500123#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
Shengzhou Liu49912402014-11-24 17:11:56 +0800124#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
125#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
126#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
Shengzhou Liu49912402014-11-24 17:11:56 +0800127
128#ifdef CONFIG_PHYS_64BIT
129#define CONFIG_SYS_DCSRBAR 0xf0000000
130#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
131#endif
132
133/* EEPROM */
Shengzhou Liu49912402014-11-24 17:11:56 +0800134#define CONFIG_SYS_I2C_EEPROM_NXID
135#define CONFIG_SYS_EEPROM_BUS_NUM 0
Shengzhou Liu49912402014-11-24 17:11:56 +0800136
137/*
138 * DDR Setup
139 */
140#define CONFIG_VERY_BIG_RAM
141#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
York Sunf9a03632016-12-28 08:43:34 -0800143#if defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800144#define CONFIG_SYS_SPD_BUS_NUM 0
145#define SPD_EEPROM_ADDRESS 0x51
Shengzhou Liu49912402014-11-24 17:11:56 +0800146#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
York Sun940ee4a2016-12-28 08:43:33 -0800147#elif defined(CONFIG_TARGET_T1023RDB)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800148#define CONFIG_SYS_DDR_RAW_TIMING
149#define CONFIG_SYS_SDRAM_SIZE 2048
150#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800151
152/*
153 * IFC Definitions
154 */
155#define CONFIG_SYS_FLASH_BASE 0xe8000000
156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
158#else
159#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
160#endif
161
162#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
163#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
164 CSPR_PORT_SIZE_16 | \
165 CSPR_MSEL_NOR | \
166 CSPR_V)
167#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
168
169/* NOR Flash Timing Params */
York Sunf9a03632016-12-28 08:43:34 -0800170#if defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800171#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
York Sun940ee4a2016-12-28 08:43:33 -0800172#elif defined(CONFIG_TARGET_T1023RDB)
Shengzhou Liu0a197892015-06-17 16:37:01 +0800173#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800174 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
175#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800176#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
177 FTIM0_NOR_TEADC(0x5) | \
178 FTIM0_NOR_TEAHC(0x5))
179#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
180 FTIM1_NOR_TRAD_NOR(0x1A) |\
181 FTIM1_NOR_TSEQRAD_NOR(0x13))
182#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
183 FTIM2_NOR_TCH(0x4) | \
184 FTIM2_NOR_TWPH(0x0E) | \
185 FTIM2_NOR_TWP(0x1c))
186#define CONFIG_SYS_NOR_FTIM3 0x0
187
188#define CONFIG_SYS_FLASH_QUIET_TEST
189#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
190
Shengzhou Liu49912402014-11-24 17:11:56 +0800191#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
192#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
194
195#define CONFIG_SYS_FLASH_EMPTY_INFO
196#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
197
York Sunf9a03632016-12-28 08:43:34 -0800198#ifdef CONFIG_TARGET_T1024RDB
Shengzhou Liu49912402014-11-24 17:11:56 +0800199/* CPLD on IFC */
200#define CONFIG_SYS_CPLD_BASE 0xffdf0000
201#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
202#define CONFIG_SYS_CSPR2_EXT (0xf)
203#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
204 | CSPR_PORT_SIZE_8 \
205 | CSPR_MSEL_GPCM \
206 | CSPR_V)
207#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
208#define CONFIG_SYS_CSOR2 0x0
209
210/* CPLD Timing parameters for IFC CS2 */
211#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
212 FTIM0_GPCM_TEADC(0x0e) | \
213 FTIM0_GPCM_TEAHC(0x0e))
214#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
215 FTIM1_GPCM_TRAD(0x1f))
216#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
217 FTIM2_GPCM_TCH(0x8) | \
218 FTIM2_GPCM_TWP(0x1f))
219#define CONFIG_SYS_CS2_FTIM3 0x0
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800220#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800221
222/* NAND Flash on IFC */
Shengzhou Liu49912402014-11-24 17:11:56 +0800223#define CONFIG_SYS_NAND_BASE 0xff800000
224#ifdef CONFIG_PHYS_64BIT
225#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
226#else
227#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
228#endif
229#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
230#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
231 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
232 | CSPR_MSEL_NAND /* MSEL = NAND */ \
233 | CSPR_V)
234#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
235
York Sunf9a03632016-12-28 08:43:34 -0800236#if defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800237#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
238 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
239 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
240 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
241 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
242 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
243 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
York Sun940ee4a2016-12-28 08:43:33 -0800244#elif defined(CONFIG_TARGET_T1023RDB)
Jaiprakash Singhc4e609f2015-05-22 15:21:07 +0530245#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800248 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
249 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
250 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
251 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800252#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800253
Shengzhou Liu49912402014-11-24 17:11:56 +0800254/* ONFI NAND Flash mode0 Timing Params */
255#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
256 FTIM0_NAND_TWP(0x18) | \
257 FTIM0_NAND_TWCHT(0x07) | \
258 FTIM0_NAND_TWH(0x0a))
259#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
260 FTIM1_NAND_TWBE(0x39) | \
261 FTIM1_NAND_TRR(0x0e) | \
262 FTIM1_NAND_TRP(0x18))
263#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
264 FTIM2_NAND_TREH(0x0a) | \
265 FTIM2_NAND_TWHRE(0x1e))
266#define CONFIG_SYS_NAND_FTIM3 0x0
267
268#define CONFIG_SYS_NAND_DDR_LAW 11
269#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
270#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu49912402014-11-24 17:11:56 +0800271
Miquel Raynald0935362019-10-03 19:50:03 +0200272#if defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liu49912402014-11-24 17:11:56 +0800273#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
274#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
275#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
276#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
277#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
278#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
279#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
280#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
281#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
282#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
283#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
284#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
285#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
286#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
287#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
288#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
289#else
290#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
291#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
292#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
293#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
294#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
295#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
296#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
297#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
298#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
299#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
300#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
301#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
302#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
303#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
304#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
305#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
306#endif
307
Shengzhou Liu49912402014-11-24 17:11:56 +0800308#if defined(CONFIG_RAMBOOT_PBL)
309#define CONFIG_SYS_RAMBOOT
310#endif
311
Shengzhou Liu49912402014-11-24 17:11:56 +0800312#define CONFIG_HWCONFIG
313
314/* define to use L1 as initial stack */
315#define CONFIG_L1_INIT_RAM
316#define CONFIG_SYS_INIT_RAM_LOCK
317#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
318#ifdef CONFIG_PHYS_64BIT
319#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700320#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu49912402014-11-24 17:11:56 +0800321/* The assembler doesn't like typecast */
322#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
323 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
324 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
325#else
York Sunee7b4832015-08-17 13:31:51 -0700326#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liu49912402014-11-24 17:11:56 +0800327#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
328#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
329#endif
330#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
331
332#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
333 GENERATED_GBL_DATA_SIZE)
334#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
335
336#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu49912402014-11-24 17:11:56 +0800337
338/* Serial Port */
Shengzhou Liu49912402014-11-24 17:11:56 +0800339#define CONFIG_SYS_NS16550_SERIAL
340#define CONFIG_SYS_NS16550_REG_SIZE 1
341#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
342
343#define CONFIG_SYS_BAUDRATE_TABLE \
344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
345
346#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
347#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
348#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
349#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Shengzhou Liu49912402014-11-24 17:11:56 +0800350
Shengzhou Liu49912402014-11-24 17:11:56 +0800351/* I2C */
Shengzhou Liu49912402014-11-24 17:11:56 +0800352
Shengzhou Liu0a197892015-06-17 16:37:01 +0800353#define I2C_PCA6408_BUS_NUM 1
354#define I2C_PCA6408_ADDR 0x20
Shengzhou Liu49912402014-11-24 17:11:56 +0800355
356/* I2C bus multiplexer */
357#define I2C_MUX_CH_DEFAULT 0x8
358
359/*
360 * RTC configuration
361 */
362#define RTC
363#define CONFIG_RTC_DS1337 1
364#define CONFIG_SYS_I2C_RTC_ADDR 0x68
365
366/*
367 * eSPI - Enhanced SPI
368 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800369
370/*
371 * General PCIe
372 * Memory space is mapped 1-1, but I/O space must start from 0.
373 */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400374#define CONFIG_PCIE1 /* PCIE controller 1 */
375#define CONFIG_PCIE2 /* PCIE controller 2 */
376#define CONFIG_PCIE3 /* PCIE controller 3 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800377
378#ifdef CONFIG_PCI
379/* controller 1, direct to uli, tgtid 3, Base address 20000 */
380#ifdef CONFIG_PCIE1
381#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Shengzhou Liu49912402014-11-24 17:11:56 +0800382#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800383#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Shengzhou Liu49912402014-11-24 17:11:56 +0800384#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800385#endif
386
387/* controller 2, Slot 2, tgtid 2, Base address 201000 */
388#ifdef CONFIG_PCIE2
389#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
Shengzhou Liu49912402014-11-24 17:11:56 +0800390#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800391#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Shengzhou Liu49912402014-11-24 17:11:56 +0800392#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800393#endif
394
395/* controller 3, Slot 1, tgtid 1, Base address 202000 */
396#ifdef CONFIG_PCIE3
397#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Shengzhou Liu49912402014-11-24 17:11:56 +0800398#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800399#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Shengzhou Liu49912402014-11-24 17:11:56 +0800400#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Shengzhou Liu49912402014-11-24 17:11:56 +0800401#endif
Hou Zhiqiang38a02b52019-08-27 11:03:34 +0000402
Shengzhou Liu49912402014-11-24 17:11:56 +0800403#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Shengzhou Liu49912402014-11-24 17:11:56 +0800404#endif /* CONFIG_PCI */
405
406/*
407 * USB
408 */
409#define CONFIG_HAS_FSL_DR_USB
410
411#ifdef CONFIG_HAS_FSL_DR_USB
Shengzhou Liu49912402014-11-24 17:11:56 +0800412#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu49912402014-11-24 17:11:56 +0800413#endif
414
415/*
416 * SDHC
417 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800418#ifdef CONFIG_MMC
Shengzhou Liu49912402014-11-24 17:11:56 +0800419#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Shengzhou Liu49912402014-11-24 17:11:56 +0800420#endif
421
422/* Qman/Bman */
423#ifndef CONFIG_NOBQFMAN
Jeffrey Ladouceurf9c39742014-12-03 18:08:43 -0500424#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liu49912402014-11-24 17:11:56 +0800425#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
428#else
429#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
430#endif
431#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500432#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
433#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
434#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
435#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
436#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
437 CONFIG_SYS_BMAN_CENA_SIZE)
438#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
439#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceurf9c39742014-12-03 18:08:43 -0500440#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liu49912402014-11-24 17:11:56 +0800441#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
442#ifdef CONFIG_PHYS_64BIT
443#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
444#else
445#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
446#endif
447#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500448#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
449#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
450#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
451#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
452#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
453 CONFIG_SYS_QMAN_CENA_SIZE)
454#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
455#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu49912402014-11-24 17:11:56 +0800456
457#define CONFIG_SYS_DPAA_FMAN
458
Shengzhou Liu49912402014-11-24 17:11:56 +0800459#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
460#endif /* CONFIG_NOBQFMAN */
461
462#ifdef CONFIG_SYS_DPAA_FMAN
York Sunf9a03632016-12-28 08:43:34 -0800463#if defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liu49912402014-11-24 17:11:56 +0800464#define RGMII_PHY1_ADDR 0x2
465#define RGMII_PHY2_ADDR 0x6
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800466#define SGMII_AQR_PHY_ADDR 0x2
Shengzhou Liu49912402014-11-24 17:11:56 +0800467#define FM1_10GEC1_PHY_ADDR 0x1
York Sun940ee4a2016-12-28 08:43:33 -0800468#elif defined(CONFIG_TARGET_T1023RDB)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800469#define RGMII_PHY1_ADDR 0x1
470#define SGMII_RTK_PHY_ADDR 0x3
471#define SGMII_AQR_PHY_ADDR 0x2
472#endif
Shengzhou Liu49912402014-11-24 17:11:56 +0800473#endif
474
Shengzhou Liu49912402014-11-24 17:11:56 +0800475/*
476 * Dynamic MTD Partition support with mtdparts
477 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800478
479/*
480 * Environment
481 */
482#define CONFIG_LOADS_ECHO /* echo on for serial download */
483#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
484
485/*
Shengzhou Liu49912402014-11-24 17:11:56 +0800486 * Miscellaneous configurable options
487 */
Shengzhou Liu49912402014-11-24 17:11:56 +0800488
489/*
490 * For booting Linux, the board info and command line data
491 * have to be in the first 64 MB of memory, since this is
492 * the maximum mapped by the Linux kernel during initialization.
493 */
494#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
495#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
496
Shengzhou Liu49912402014-11-24 17:11:56 +0800497/*
498 * Environment Configuration
499 */
500#define CONFIG_ROOTPATH "/opt/nfsroot"
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800501#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Shengzhou Liu49912402014-11-24 17:11:56 +0800502#define __USB_PHY_TYPE utmi
503
York Sun7d29dd62016-11-18 13:01:34 -0800504#ifdef CONFIG_ARCH_T1024
Tom Rini272eb5b2022-03-21 21:33:32 -0400505#define ARCH_EXTRA_ENV_SETTINGS \
506 "bank_intlv=cs0_cs1\0" \
507 "ramdiskfile=t1024rdb/ramdisk.uboot\0" \
508 "fdtfile=t1024rdb/t1024rdb.dtb\0"
Shengzhou Liu49912402014-11-24 17:11:56 +0800509#else
Tom Rini272eb5b2022-03-21 21:33:32 -0400510#define ARCH_EXTRA_ENV_SETTINGS \
511 "bank_intlv=null\0" \
512 "ramdiskfile=t1023rdb/ramdisk.uboot\0" \
513 "fdtfile=t1023rdb/t1023rdb.dtb\0"
Shengzhou Liu49912402014-11-24 17:11:56 +0800514#endif
515
516#define CONFIG_EXTRA_ENV_SETTINGS \
Tom Rini272eb5b2022-03-21 21:33:32 -0400517 ARCH_EXTRA_ENV_SETTINGS \
Shengzhou Liu49912402014-11-24 17:11:56 +0800518 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Shengzhou Liu49912402014-11-24 17:11:56 +0800519 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
Shengzhou Liu49912402014-11-24 17:11:56 +0800520 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
521 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
522 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
523 "netdev=eth0\0" \
524 "tftpflash=tftpboot $loadaddr $uboot && " \
525 "protect off $ubootaddr +$filesize && " \
526 "erase $ubootaddr +$filesize && " \
527 "cp.b $loadaddr $ubootaddr $filesize && " \
528 "protect on $ubootaddr +$filesize && " \
529 "cmp.b $loadaddr $ubootaddr $filesize\0" \
530 "consoledev=ttyS0\0" \
531 "ramdiskaddr=2000000\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500532 "fdtaddr=1e00000\0" \
Shengzhou Liu49912402014-11-24 17:11:56 +0800533 "bdev=sda3\0"
534
Shengzhou Liu49912402014-11-24 17:11:56 +0800535#include <asm/fsl_secure_boot.h>
Aneesh Bansal962021a2016-01-22 16:37:22 +0530536
Shengzhou Liu49912402014-11-24 17:11:56 +0800537#endif /* __T1024RDB_H */