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Srinath714194e2011-04-18 17:40:35 -04001/*
2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3 *
4 * Author: Srinath.R <srinath@mistralsolutions.com>
5 *
6 * Based on include/configs/am3517evm.h
7 *
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Srinath714194e2011-04-18 17:40:35 -040011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Srinath714194e2011-04-18 17:40:35 -040019#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
20
21#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050022#include <asm/arch/omap.h>
Srinath714194e2011-04-18 17:40:35 -040023
Srinath714194e2011-04-18 17:40:35 -040024/* Clock Defines */
25#define V_OSCK 26000000 /* Clock output from T2 */
26#define V_SCLK (V_OSCK >> 1)
27
Srinath714194e2011-04-18 17:40:35 -040028#define CONFIG_MISC_INIT_R
29
30#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
31#define CONFIG_SETUP_MEMORY_TAGS 1
32#define CONFIG_INITRD_TAG 1
33#define CONFIG_REVISION_TAG 1
34
35/*
36 * Size of malloc() pool
37 */
38#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
39#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
40 /* initial data */
41/*
42 * DDR related
43 */
Srinath714194e2011-04-18 17:40:35 -040044#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
45
46/*
47 * Hardware drivers
48 */
49
50/*
51 * NS16550 Configuration
52 */
53#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
54
Srinath714194e2011-04-18 17:40:35 -040055#define CONFIG_SYS_NS16550_SERIAL
56#define CONFIG_SYS_NS16550_REG_SIZE (-4)
57#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
58
59/*
60 * select serial console configuration
61 */
62#define CONFIG_CONS_INDEX 3
63#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
64#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
65
66/* allow to overwrite serial and ethaddr */
67#define CONFIG_ENV_OVERWRITE
Srinath714194e2011-04-18 17:40:35 -040068#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
69 115200}
Srinath714194e2011-04-18 17:40:35 -040070
71/*
72 * USB configuration
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020073 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
74 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
Srinath714194e2011-04-18 17:40:35 -040075 */
76#define CONFIG_USB_AM35X 1
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020077#define CONFIG_USB_MUSB_HCD 1
Srinath714194e2011-04-18 17:40:35 -040078
79#ifdef CONFIG_USB_AM35X
80
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020081#ifdef CONFIG_USB_MUSB_HCD
Srinath714194e2011-04-18 17:40:35 -040082
Srinath714194e2011-04-18 17:40:35 -040083#ifdef CONFIG_USB_KEYBOARD
84#define CONFIG_SYS_USB_EVENT_POLL
85#define CONFIG_PREBOOT "usb start"
86#endif /* CONFIG_USB_KEYBOARD */
87
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020088#endif /* CONFIG_USB_MUSB_HCD */
Srinath714194e2011-04-18 17:40:35 -040089
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020090#ifdef CONFIG_USB_MUSB_UDC
Srinath714194e2011-04-18 17:40:35 -040091/* USB device configuration */
92#define CONFIG_USB_DEVICE 1
93#define CONFIG_USB_TTY 1
Srinath714194e2011-04-18 17:40:35 -040094/* Change these to suit your needs */
95#define CONFIG_USBD_VENDORID 0x0451
96#define CONFIG_USBD_PRODUCTID 0x5678
97#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
98#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020099#endif /* CONFIG_USB_MUSB_UDC */
Srinath714194e2011-04-18 17:40:35 -0400100
101#endif /* CONFIG_USB_AM35X */
102
103/* commands to include */
Srinath714194e2011-04-18 17:40:35 -0400104
Srinath714194e2011-04-18 17:40:35 -0400105#define CONFIG_CMD_NAND /* NAND support */
Srinath714194e2011-04-18 17:40:35 -0400106
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200107#define CONFIG_SYS_I2C
108#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
109#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
110#define CONFIG_SYS_I2C_OMAP34XX
Srinath714194e2011-04-18 17:40:35 -0400111
Srinath714194e2011-04-18 17:40:35 -0400112/*
113 * Board NAND Info.
114 */
115#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
116 /* to access nand */
117#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
118 /* to access */
119 /* nand at CS0 */
120
121#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
122 /* NAND devices */
Srinath714194e2011-04-18 17:40:35 -0400123
124#define CONFIG_JFFS2_NAND
125/* nand device jffs2 lives on */
126#define CONFIG_JFFS2_DEV "nand0"
127/* start of jffs2 partition */
128#define CONFIG_JFFS2_PART_OFFSET 0x680000
129#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
130
131/* Environment information */
Srinath714194e2011-04-18 17:40:35 -0400132
Joe Hershbergere4da2482011-10-13 13:03:48 +0000133#define CONFIG_BOOTFILE "uImage"
Srinath714194e2011-04-18 17:40:35 -0400134
135#define CONFIG_EXTRA_ENV_SETTINGS \
136 "loadaddr=0x82000000\0" \
137 "console=ttyS2,115200n8\0" \
Tom Rini54c0b7b2011-09-03 21:51:50 -0400138 "mmcdev=0\0" \
Srinath714194e2011-04-18 17:40:35 -0400139 "mmcargs=setenv bootargs console=${console} " \
140 "root=/dev/mmcblk0p2 rw " \
141 "rootfstype=ext3 rootwait\0" \
142 "nandargs=setenv bootargs console=${console} " \
143 "root=/dev/mtdblock4 rw " \
144 "rootfstype=jffs2\0" \
Tom Rini54c0b7b2011-09-03 21:51:50 -0400145 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Srinath714194e2011-04-18 17:40:35 -0400146 "bootscript=echo Running bootscript from mmc ...; " \
147 "source ${loadaddr}\0" \
Tom Rini54c0b7b2011-09-03 21:51:50 -0400148 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Srinath714194e2011-04-18 17:40:35 -0400149 "mmcboot=echo Booting from mmc ...; " \
150 "run mmcargs; " \
151 "bootm ${loadaddr}\0" \
152 "nandboot=echo Booting from nand ...; " \
153 "run nandargs; " \
154 "nand read ${loadaddr} 280000 400000; " \
155 "bootm ${loadaddr}\0" \
156
157#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +0000158 "mmc dev ${mmcdev}; if mmc rescan; then " \
Srinath714194e2011-04-18 17:40:35 -0400159 "if run loadbootscript; then " \
160 "run bootscript; " \
161 "else " \
162 "if run loaduimage; then " \
163 "run mmcboot; " \
164 "else run nandboot; " \
165 "fi; " \
166 "fi; " \
167 "else run nandboot; fi"
168
169#define CONFIG_AUTO_COMPLETE 1
170/*
171 * Miscellaneous configurable options
172 */
Srinath714194e2011-04-18 17:40:35 -0400173#define CONFIG_SYS_LONGHELP /* undef to save memory */
Srinath714194e2011-04-18 17:40:35 -0400174#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
175/* Print Buffer Size */
176#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
177 sizeof(CONFIG_SYS_PROMPT) + 16)
178#define CONFIG_SYS_MAXARGS 32 /* max number of command */
179 /* args */
180/* Boot Argument Buffer Size */
181#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
182/* memtest works on */
183#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
184#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
185 0x01F00000) /* 31MB */
186
187#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
188 /* address */
189
190/*
191 * AM3517 has 12 GP timers, they can be driven by the system clock
192 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
193 * This rate is divided by a local divisor.
194 */
195#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
196#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Srinath714194e2011-04-18 17:40:35 -0400197
198/*-----------------------------------------------------------------------
Srinath714194e2011-04-18 17:40:35 -0400199 * Physical Memory Map
200 */
201#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
202#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Srinath714194e2011-04-18 17:40:35 -0400203#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
204
Srinath714194e2011-04-18 17:40:35 -0400205/*-----------------------------------------------------------------------
206 * FLASH and environment organization
207 */
208
209/* **** PISMO SUPPORT *** */
Srinath714194e2011-04-18 17:40:35 -0400210#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
211 /* on one chip */
212#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
213#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
214
pekon gupta0a9ec452014-07-18 17:59:41 +0530215#define CONFIG_SYS_FLASH_BASE NAND_BASE
Srinath714194e2011-04-18 17:40:35 -0400216
217/* Monitor at start of flash */
218#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
219
220#define CONFIG_NAND_OMAP_GPMC
Srinath714194e2011-04-18 17:40:35 -0400221#define CONFIG_ENV_IS_IN_NAND 1
222#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
223
Luca Ceresoli9783a2c2011-04-20 11:02:05 -0400224#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
225#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
226#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
Srinath714194e2011-04-18 17:40:35 -0400227
228/*-----------------------------------------------------------------------
229 * CFI FLASH driver setup
230 */
231/* timeout values are in ticks */
232#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
233#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
234
235/* Flash banks JFFS2 should use */
236#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
237 CONFIG_SYS_MAX_NAND_DEVICE)
238#define CONFIG_SYS_JFFS2_MEM_NAND
239/* use flash_info[2] */
240#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
241#define CONFIG_SYS_JFFS2_NUM_BANKS 1
242
Srinath714194e2011-04-18 17:40:35 -0400243#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
244#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
245#define CONFIG_SYS_INIT_RAM_SIZE 0x800
246#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
247 CONFIG_SYS_INIT_RAM_SIZE - \
248 GENERATED_GBL_DATA_SIZE)
Tom Rini9e341852011-11-18 12:48:11 +0000249
250/* Defines for SPL */
Tom Rini28591df2012-08-13 12:03:19 -0700251#define CONFIG_SPL_FRAMEWORK
Tom Rini9e341852011-11-18 12:48:11 +0000252#define CONFIG_SPL_NAND_SIMPLE
253#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinicfff4aa2016-08-26 13:30:43 -0400254#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
255 CONFIG_SPL_TEXT_BASE)
Tom Rini9e341852011-11-18 12:48:11 +0000256
257#define CONFIG_SPL_BSS_START_ADDR 0x80000000
258#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
259
Paul Kocialkowski341e8cd2014-11-08 23:14:55 +0100260#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200261#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Tom Rini9e341852011-11-18 12:48:11 +0000262
Scott Woodc352a0c2012-09-20 19:09:07 -0500263#define CONFIG_SPL_NAND_BASE
264#define CONFIG_SPL_NAND_DRIVERS
265#define CONFIG_SPL_NAND_ECC
Tom Rini28eec372016-11-07 21:34:54 -0500266#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
Tom Rini9e341852011-11-18 12:48:11 +0000267
268/* NAND boot config */
Stefano Babic0cd41182015-07-26 15:18:15 +0200269#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Tom Rini9e341852011-11-18 12:48:11 +0000270#define CONFIG_SYS_NAND_5_ADDR_CYCLE
271#define CONFIG_SYS_NAND_PAGE_COUNT 64
272#define CONFIG_SYS_NAND_PAGE_SIZE 2048
273#define CONFIG_SYS_NAND_OOBSIZE 64
274#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
275#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
276#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
277 10, 11, 12, 13}
278#define CONFIG_SYS_NAND_ECCSIZE 512
279#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3ef49732013-11-18 19:03:01 +0530280#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
Tom Rini9e341852011-11-18 12:48:11 +0000281#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
282#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
283
284/*
285 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
286 * 64 bytes before this address should be set aside for u-boot.img's
287 * header. That is 0x800FFFC0--0x80100000 should not be used for any
288 * other needs.
289 */
290#define CONFIG_SYS_TEXT_BASE 0x80100000
291#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
292#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
293
Srinath714194e2011-04-18 17:40:35 -0400294#endif /* __CONFIG_H */