Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 55a99219b496bfe32d867db76645b841def9ee8f / . / include / configs / UCP1020.h
blob: 9a7aa811963c63353796033aaea238be093e39d4 [file] [log] [blame]
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]1/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]17#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
18#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
19#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
20#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
21#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
22#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
23
24#if defined(CONFIG_TARTGET_UCP1020T1)
25
26#define CONFIG_UCP1020_REV_1_3
27
28#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]29
30#define CONFIG_TSEC_ENET
31#define CONFIG_TSEC1
32#define CONFIG_TSEC3
33#define CONFIG_HAS_ETH0
34#define CONFIG_HAS_ETH1
35#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
36#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
37#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
38#define CONFIG_IPADDR 10.80.41.229
39#define CONFIG_SERVERIP 10.80.41.227
40#define CONFIG_NETMASK 255.255.252.0
41#define CONFIG_ETHPRIME "eTSEC3"
42
43#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]44#endif
45#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
46
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]47#define CONFIG_SYS_L2_SIZE (256 << 10)
48
49#define CONFIG_LAST_STAGE_INIT
50
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]51#endif
52
53#if defined(CONFIG_TARGET_UCP1020)
54
55#define CONFIG_UCP1020
56#define CONFIG_UCP1020_REV_1_3
57
58#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]59
60#define CONFIG_TSEC_ENET
61#define CONFIG_TSEC1
62#define CONFIG_TSEC2
63#define CONFIG_TSEC3
64#define CONFIG_HAS_ETH0
65#define CONFIG_HAS_ETH1
66#define CONFIG_HAS_ETH2
67#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
68#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
69#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
70#define CONFIG_IPADDR 192.168.1.81
71#define CONFIG_IPADDR1 192.168.1.82
72#define CONFIG_IPADDR2 192.168.1.83
73#define CONFIG_SERVERIP 192.168.1.80
74#define CONFIG_GATEWAYIP 102.168.1.1
75#define CONFIG_NETMASK 255.255.255.0
76#define CONFIG_ETHPRIME "eTSEC1"
77
78#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]79#endif
80#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
81
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]82#define CONFIG_SYS_L2_SIZE (256 << 10)
83
84#define CONFIG_LAST_STAGE_INIT
85
86#endif
87
88#ifdef CONFIG_SDCARD
89#define CONFIG_RAMBOOT_SDCARD
90#define CONFIG_SYS_RAMBOOT
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_SYS_TEXT_BASE 0x11000000
93#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
94#endif
95
96#ifdef CONFIG_SPIFLASH
97#define CONFIG_RAMBOOT_SPIFLASH
98#define CONFIG_SYS_RAMBOOT
99#define CONFIG_SYS_EXTRA_ENV_RELOC
100#define CONFIG_SYS_TEXT_BASE 0x11000000
101#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
102#endif
103
104#ifndef CONFIG_SYS_TEXT_BASE
105#define CONFIG_SYS_TEXT_BASE 0xeff80000
106#endif
107#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
108
109#ifndef CONFIG_RESET_VECTOR_ADDRESS
110#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
111#endif
112
113#ifndef CONFIG_SYS_MONITOR_BASE
114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
115#endif
116
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]117#define CONFIG_MP
118
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]119#define CONFIG_ENV_OVERWRITE
120
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]121#define CONFIG_SATA_SIL
122#define CONFIG_SYS_SATA_MAX_DEVICE 2
123#define CONFIG_LIBATA
124#define CONFIG_LBA48
125
126#define CONFIG_SYS_CLK_FREQ 66666666
127#define CONFIG_DDR_CLK_FREQ 66666666
128
129#define CONFIG_HWCONFIG
130
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]131/*
132 * These can be toggled for performance analysis, otherwise use default.
133 */
134#define CONFIG_L2_CACHE
135#define CONFIG_BTB
136
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]137#define CONFIG_ENABLE_36BIT_PHYS
138
139#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x1fffffff
141#define CONFIG_PANIC_HANG /* do not reset board on panic */
142
143#define CONFIG_SYS_CCSRBAR 0xffe00000
144#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
145
146/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
147 SPL code*/
148#ifdef CONFIG_SPL_BUILD
149#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
150#endif
151
152/* DDR Setup */
153#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]154#ifndef CONFIG_DDR_ECC_ENABLE
155#define CONFIG_SYS_DDR_RAW_TIMING
156#define CONFIG_DDR_SPD
157#endif
158#define CONFIG_SYS_SPD_BUS_NUM 1
159#undef CONFIG_FSL_DDR_INTERACTIVE
160
161#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
162#define CONFIG_CHIP_SELECTS_PER_CTRL 1
163#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
164#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
165#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]167#define CONFIG_DIMM_SLOTS_PER_CTLR 1
168
169/* Default settings for DDR3 */
170#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
171#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
172#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
173#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
174#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
175#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
176
177#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
178#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
179#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
180#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
181
182#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
183#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
184#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
185#define CONFIG_SYS_DDR_RCW_1 0x00000000
186#define CONFIG_SYS_DDR_RCW_2 0x00000000
187#ifdef CONFIG_DDR_ECC_ENABLE
188#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
189#else
190#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
191#endif
192#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
193#define CONFIG_SYS_DDR_TIMING_4 0x00220001
194#define CONFIG_SYS_DDR_TIMING_5 0x03402400
195
196#define CONFIG_SYS_DDR_TIMING_3 0x00020000
197#define CONFIG_SYS_DDR_TIMING_0 0x00330004
198#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
199#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
200#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
201#define CONFIG_SYS_DDR_MODE_1 0x40461520
202#define CONFIG_SYS_DDR_MODE_2 0x8000c000
203#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
204
205#undef CONFIG_CLOCKS_IN_MHZ
206
207/*
208 * Memory map
209 *
210 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
211 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
212 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
213 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
214 * (early boot only)
215 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
216 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
217 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
218 */
219
220/*
221 * Local Bus Definitions
222 */
223#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
224#define CONFIG_SYS_FLASH_BASE 0xec000000
225
226#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
227
228#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
229 | BR_PS_16 | BR_V)
230
231#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
232
233#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
234#define CONFIG_SYS_FLASH_QUIET_TEST
235#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
236
237#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
238
239#undef CONFIG_SYS_FLASH_CHECKSUM
240#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
241#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
242
243#define CONFIG_FLASH_CFI_DRIVER
244#define CONFIG_SYS_FLASH_CFI
245#define CONFIG_SYS_FLASH_EMPTY_INFO
246#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
247
248#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
249
250#define CONFIG_SYS_INIT_RAM_LOCK
251#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
252/* Initial L1 address */
253#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
254#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
255#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
256/* Size of used area in RAM */
257#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
258
259#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
260 GENERATED_GBL_DATA_SIZE)
261#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
262
263#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
264#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
265
266#define CONFIG_SYS_PMC_BASE 0xff980000
267#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
268#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
269 BR_PS_8 | BR_V)
270#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
271 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
272 OR_GPCM_EAD)
273
274#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
275#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
276#ifdef CONFIG_NAND_FSL_ELBC
277#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
278#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
279#endif
280
281/* Serial Port - controlled on board with jumper J8
282 * open - index 2
283 * shorted - index 1
284 */
285#define CONFIG_CONS_INDEX 1
286#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]287#define CONFIG_SYS_NS16550_SERIAL
288#define CONFIG_SYS_NS16550_REG_SIZE 1
289#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
290#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
291#define CONFIG_NS16550_MIN_FUNCTIONS
292#endif
293
294#define CONFIG_SYS_BAUDRATE_TABLE \
295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
296
297#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
298#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
299
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]300/* I2C */
301#define CONFIG_SYS_I2C
302#define CONFIG_SYS_I2C_FSL
303#define CONFIG_SYS_FSL_I2C_SPEED 400000
304#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
305#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
306#define CONFIG_SYS_FSL_I2C2_SPEED 400000
307#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
308#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
309#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
310#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
311
312#define CONFIG_RTC_DS1337
Chris Packham2d3ac512017-05-30 12:03:33 +1200[diff] [blame]313#define CONFIG_RTC_DS1337_NOOSC
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]314#define CONFIG_SYS_I2C_RTC_ADDR 0x68
315#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
316#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
317#define CONFIG_SYS_I2C_IDT6V49205B 0x69
318
319/*
320 * eSPI - Enhanced SPI
321 */
322#define CONFIG_HARD_SPI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]323
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]324#define CONFIG_SF_DEFAULT_SPEED 10000000
325#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
326
327#if defined(CONFIG_PCI)
328/*
329 * General PCI
330 * Memory space is mapped 1-1, but I/O space must start from 0.
331 */
332
333/* controller 2, direct to uli, tgtid 2, Base address 9000 */
334#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
335#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
336#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
337#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
338#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
339#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
340#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
341#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
342#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
343
344/* controller 1, Slot 2, tgtid 1, Base address a000 */
345#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
346#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
347#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
348#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
349#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
350#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
351#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
352#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
353#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
354
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]355#define CONFIG_CMD_PCI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]356
357#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]358#endif /* CONFIG_PCI */
359
360/*
361 * Environment
362 */
363#ifdef CONFIG_ENV_FIT_UCBOOT
364
365#define CONFIG_ENV_IS_IN_FLASH
366#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
367#define CONFIG_ENV_SIZE 0x20000
368#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
369
370#else
371
372#define CONFIG_ENV_SPI_BUS 0
373#define CONFIG_ENV_SPI_CS 0
374#define CONFIG_ENV_SPI_MAX_HZ 10000000
375#define CONFIG_ENV_SPI_MODE 0
376
377#ifdef CONFIG_RAMBOOT_SPIFLASH
378
379#define CONFIG_ENV_IS_IN_SPI_FLASH
380#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
381#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
382#define CONFIG_ENV_SECT_SIZE 0x1000
383
384#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
385/* Address and size of Redundant Environment Sector */
386#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
387#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
388#endif
389
390#elif defined(CONFIG_RAMBOOT_SDCARD)
391#define CONFIG_ENV_IS_IN_MMC
392#define CONFIG_FSL_FIXED_MMC_LOCATION
393#define CONFIG_ENV_SIZE 0x2000
394#define CONFIG_SYS_MMC_ENV_DEV 0
395
396#elif defined(CONFIG_SYS_RAMBOOT)
397#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
398#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
399#define CONFIG_ENV_SIZE 0x2000
400
401#else
402#define CONFIG_ENV_IS_IN_FLASH
403#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
404#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
405#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
406#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
407#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
408/* Address and size of Redundant Environment Sector */
409#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
410#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
411#endif
412
413#endif
414
415#endif /* CONFIG_ENV_FIT_UCBOOT */
416
417#define CONFIG_LOADS_ECHO /* echo on for serial download */
418#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
419
420/*
421 * Command line configuration.
422 */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]423#define CONFIG_CMD_REGINFO
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]424
425/*
426 * USB
427 */
428#define CONFIG_HAS_FSL_DR_USB
429
430#if defined(CONFIG_HAS_FSL_DR_USB)
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]431#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
432
Tom Riniceed5d22017-05-12 22:33:27 -0400[diff] [blame]433#ifdef CONFIG_USB_EHCI_HCD
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]434#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
435#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]436#endif
437#endif
438
439#undef CONFIG_WATCHDOG /* watchdog disabled */
440
441#ifdef CONFIG_MMC
442#define CONFIG_FSL_ESDHC
443#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]444#define CONFIG_MMC_SPI
445#define CONFIG_CMD_MMC_SPI
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]446#endif
447
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]448/* Misc Extra Settings */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]449#undef CONFIG_WATCHDOG /* watchdog disabled */
450
451/*
452 * Miscellaneous configurable options
453 */
454#define CONFIG_SYS_LONGHELP /* undef to save memory */
455#define CONFIG_CMDLINE_EDITING /* Command-line editing */
456#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]457#if defined(CONFIG_CMD_KGDB)
458#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
459#else
460#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
461#endif
462#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
463 /* Print Buffer Size */
464#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
465#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
466#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
467
468/*
469 * For booting Linux, the board info and command line data
470 * have to be in the first 64 MB of memory, since this is
471 * the maximum mapped by the Linux kernel during initialization.
472 */
473#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
474#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
475
476#if defined(CONFIG_CMD_KGDB)
477#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
478#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
479#endif
480
481/*
482 * Environment Configuration
483 */
484
485#if defined(CONFIG_TSEC_ENET)
486
487#if defined(CONFIG_UCP1020_REV_1_2)
488#define CONFIG_PHY_MICREL_KSZ9021
489#elif defined(CONFIG_UCP1020_REV_1_3)
490#define CONFIG_PHY_MICREL_KSZ9031
491#else
492#error "UCP1020 module revision is not defined !!!"
493#endif
494
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]495#define CONFIG_BOOTP_SERVERIP
496
497#define CONFIG_MII /* MII PHY management */
498#define CONFIG_TSEC1_NAME "eTSEC1"
499#define CONFIG_TSEC2_NAME "eTSEC2"
500#define CONFIG_TSEC3_NAME "eTSEC3"
501
502#define TSEC1_PHY_ADDR 4
503#define TSEC2_PHY_ADDR 0
504#define TSEC2_PHY_ADDR_SGMII 0x00
505#define TSEC3_PHY_ADDR 6
506
507#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
508#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
509#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
510
511#define TSEC1_PHYIDX 0
512#define TSEC2_PHYIDX 0
513#define TSEC3_PHYIDX 0
514
515#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
516
517#endif
518
519#define CONFIG_HOSTNAME UCP1020
520#define CONFIG_ROOTPATH "/opt/nfsroot"
521#define CONFIG_BOOTFILE "uImage"
522#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
523
524/* default location for tftp and bootm */
525#define CONFIG_LOADADDR 1000000
526
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]527#define CONFIG_BOOTARGS /* the boot command will set bootargs */
528
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]529#if defined(CONFIG_DONGLE)
530
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]531#define CONFIG_EXTRA_ENV_SETTINGS \
532"bootcmd=run prog_spi_mbrbootcramfs\0" \
533"bootfile=uImage\0" \
534"consoledev=ttyS0\0" \
535"cramfsfile=image.cramfs\0" \
536"dtbaddr=0x00c00000\0" \
537"dtbfile=image.dtb\0" \
538"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
539"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
540"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
541"fileaddr=0x01000000\0" \
542"filesize=0x00080000\0" \
543"flashmbr=sf probe 0; " \
544 "tftp $loadaddr $mbr; " \
545 "sf erase $mbr_offset +$filesize; " \
546 "sf write $loadaddr $mbr_offset $filesize\0" \
547"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
548 "protect off $nor_recoveryaddr +$filesize; " \
549 "erase $nor_recoveryaddr +$filesize; " \
550 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
551 "protect on $nor_recoveryaddr +$filesize\0 " \
552"flashuboot=tftp $ubootaddr $ubootfile; " \
553 "protect off $nor_ubootaddr +$filesize; " \
554 "erase $nor_ubootaddr +$filesize; " \
555 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
556 "protect on $nor_ubootaddr +$filesize\0 " \
557"flashworking=tftp $workingaddr $cramfsfile; " \
558 "protect off $nor_workingaddr +$filesize; " \
559 "erase $nor_workingaddr +$filesize; " \
560 "cp.b $workingaddr $nor_workingaddr $filesize; " \
561 "protect on $nor_workingaddr +$filesize\0 " \
562"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
563"kerneladdr=0x01100000\0" \
564"kernelfile=uImage\0" \
565"loadaddr=0x01000000\0" \
566"mbr=uCP1020d.mbr\0" \
567"mbr_offset=0x00000000\0" \
568"mmbr=uCP1020Quiet.mbr\0" \
569"mmcpart=0:2\0" \
570"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
571 "mmc erase 1 1; " \
572 "mmc write $loadaddr 1 1\0" \
573"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
574 "mmc erase 0x40 0x400; " \
575 "mmc write $loadaddr 0x40 0x400\0" \
576"netdev=eth0\0" \
577"nor_recoveryaddr=0xEC0A0000\0" \
578"nor_ubootaddr=0xEFF80000\0" \
579"nor_workingaddr=0xECFA0000\0" \
580"norbootrecovery=setenv bootargs $recoverybootargs" \
581 " console=$consoledev,$baudrate $othbootargs; " \
582 "run norloadrecovery; " \
583 "bootm $kerneladdr - $dtbaddr\0" \
584"norbootworking=setenv bootargs $workingbootargs" \
585 " console=$consoledev,$baudrate $othbootargs; " \
586 "run norloadworking; " \
587 "bootm $kerneladdr - $dtbaddr\0" \
588"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
589 "setenv cramfsaddr $nor_recoveryaddr; " \
590 "cramfsload $dtbaddr $dtbfile; " \
591 "cramfsload $kerneladdr $kernelfile\0" \
592"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
593 "setenv cramfsaddr $nor_workingaddr; " \
594 "cramfsload $dtbaddr $dtbfile; " \
595 "cramfsload $kerneladdr $kernelfile\0" \
596"prog_spi_mbr=run spi__mbr\0" \
597"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
598"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
599 "run spi__cramfs\0" \
600"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
601 " console=$consoledev,$baudrate $othbootargs; " \
602 "tftp $rootfsaddr $rootfsfile; " \
603 "tftp $loadaddr $kernelfile; " \
604 "tftp $dtbaddr $dtbfile; " \
605 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
606"ramdisk_size=120000\0" \
607"ramdiskfile=rootfs.ext2.gz.uboot\0" \
608"recoveryaddr=0x02F00000\0" \
609"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
610"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
611 "mw.l 0xffe0f008 0x00400000\0" \
612"rootfsaddr=0x02F00000\0" \
613"rootfsfile=rootfs.ext2.gz.uboot\0" \
614"rootpath=/opt/nfsroot\0" \
615"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
616 "protect off 0xeC000000 +$filesize; " \
617 "erase 0xEC000000 +$filesize; " \
618 "cp.b $loadaddr 0xEC000000 $filesize; " \
619 "cmp.b $loadaddr 0xEC000000 $filesize; " \
620 "protect on 0xeC000000 +$filesize\0" \
621"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
622 "protect off 0xeFF80000 +$filesize; " \
623 "erase 0xEFF80000 +$filesize; " \
624 "cp.b $loadaddr 0xEFF80000 $filesize; " \
625 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
626 "protect on 0xeFF80000 +$filesize\0" \
627"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
628 "sf probe 0; sf erase 0x8000 +$filesize; " \
629 "sf write $loadaddr 0x8000 $filesize\0" \
630"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
631 "protect off 0xec0a0000 +$filesize; " \
632 "erase 0xeC0A0000 +$filesize; " \
633 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
634 "protect on 0xec0a0000 +$filesize\0" \
635"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
636 "sf probe 1; sf erase 0 +$filesize; " \
637 "sf write $loadaddr 0 $filesize\0" \
638"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
639 "sf probe 0; sf erase 0 +$filesize; " \
640 "sf write $loadaddr 0 $filesize\0" \
641"tftpflash=tftpboot $loadaddr $uboot; " \
642 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
643 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
644 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
645 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
646 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
647"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
648"ubootaddr=0x01000000\0" \
649"ubootfile=u-boot.bin\0" \
650"ubootd=u-boot4dongle.bin\0" \
651"upgrade=run flashworking\0" \
652"usb_phy_type=ulpi\0 " \
653"workingaddr=0x02F00000\0" \
654"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
655
656#else
657
658#if defined(CONFIG_UCP1020T1)
659
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]660#define CONFIG_EXTRA_ENV_SETTINGS \
661"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
662"bootfile=uImage\0" \
663"consoledev=ttyS0\0" \
664"cramfsfile=image.cramfs\0" \
665"dtbaddr=0x00c00000\0" \
666"dtbfile=image.dtb\0" \
667"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
668"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
669"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
670"fileaddr=0x01000000\0" \
671"filesize=0x00080000\0" \
672"flashmbr=sf probe 0; " \
673 "tftp $loadaddr $mbr; " \
674 "sf erase $mbr_offset +$filesize; " \
675 "sf write $loadaddr $mbr_offset $filesize\0" \
676"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
677 "protect off $nor_recoveryaddr +$filesize; " \
678 "erase $nor_recoveryaddr +$filesize; " \
679 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
680 "protect on $nor_recoveryaddr +$filesize\0 " \
681"flashuboot=tftp $ubootaddr $ubootfile; " \
682 "protect off $nor_ubootaddr +$filesize; " \
683 "erase $nor_ubootaddr +$filesize; " \
684 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
685 "protect on $nor_ubootaddr +$filesize\0 " \
686"flashworking=tftp $workingaddr $cramfsfile; " \
687 "protect off $nor_workingaddr +$filesize; " \
688 "erase $nor_workingaddr +$filesize; " \
689 "cp.b $workingaddr $nor_workingaddr $filesize; " \
690 "protect on $nor_workingaddr +$filesize\0 " \
691"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
692"kerneladdr=0x01100000\0" \
693"kernelfile=uImage\0" \
694"loadaddr=0x01000000\0" \
695"mbr=uCP1020.mbr\0" \
696"mbr_offset=0x00000000\0" \
697"netdev=eth0\0" \
698"nor_recoveryaddr=0xEC0A0000\0" \
699"nor_ubootaddr=0xEFF80000\0" \
700"nor_workingaddr=0xECFA0000\0" \
701"norbootrecovery=setenv bootargs $recoverybootargs" \
702 " console=$consoledev,$baudrate $othbootargs; " \
703 "run norloadrecovery; " \
704 "bootm $kerneladdr - $dtbaddr\0" \
705"norbootworking=setenv bootargs $workingbootargs" \
706 " console=$consoledev,$baudrate $othbootargs; " \
707 "run norloadworking; " \
708 "bootm $kerneladdr - $dtbaddr\0" \
709"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
710 "setenv cramfsaddr $nor_recoveryaddr; " \
711 "cramfsload $dtbaddr $dtbfile; " \
712 "cramfsload $kerneladdr $kernelfile\0" \
713"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
714 "setenv cramfsaddr $nor_workingaddr; " \
715 "cramfsload $dtbaddr $dtbfile; " \
716 "cramfsload $kerneladdr $kernelfile\0" \
717"othbootargs=quiet\0" \
718"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
719 " console=$consoledev,$baudrate $othbootargs; " \
720 "tftp $rootfsaddr $rootfsfile; " \
721 "tftp $loadaddr $kernelfile; " \
722 "tftp $dtbaddr $dtbfile; " \
723 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
724"ramdisk_size=120000\0" \
725"ramdiskfile=rootfs.ext2.gz.uboot\0" \
726"recoveryaddr=0x02F00000\0" \
727"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
728"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
729 "mw.l 0xffe0f008 0x00400000\0" \
730"rootfsaddr=0x02F00000\0" \
731"rootfsfile=rootfs.ext2.gz.uboot\0" \
732"rootpath=/opt/nfsroot\0" \
733"silent=1\0" \
734"tftpflash=tftpboot $loadaddr $uboot; " \
735 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
736 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
737 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
738 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
739 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
740"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
741"ubootaddr=0x01000000\0" \
742"ubootfile=u-boot.bin\0" \
743"upgrade=run flashworking\0" \
744"workingaddr=0x02F00000\0" \
745"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
746
747#else /* For Arcturus Modules */
748
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -0400[diff] [blame]749#define CONFIG_EXTRA_ENV_SETTINGS \
750"bootcmd=run norkernel\0" \
751"bootfile=uImage\0" \
752"consoledev=ttyS0\0" \
753"dtbaddr=0x00c00000\0" \
754"dtbfile=image.dtb\0" \
755"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
756"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
757"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
758"fileaddr=0x01000000\0" \
759"filesize=0x00080000\0" \
760"flashmbr=sf probe 0; " \
761 "tftp $loadaddr $mbr; " \
762 "sf erase $mbr_offset +$filesize; " \
763 "sf write $loadaddr $mbr_offset $filesize\0" \
764"flashuboot=tftp $loadaddr $ubootfile; " \
765 "protect off $nor_ubootaddr0 +$filesize; " \
766 "erase $nor_ubootaddr0 +$filesize; " \
767 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
768 "protect on $nor_ubootaddr0 +$filesize; " \
769 "protect off $nor_ubootaddr1 +$filesize; " \
770 "erase $nor_ubootaddr1 +$filesize; " \
771 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
772 "protect on $nor_ubootaddr1 +$filesize\0 " \
773"format0=protect off $part0base +$part0size; " \
774 "erase $part0base +$part0size\0" \
775"format1=protect off $part1base +$part1size; " \
776 "erase $part1base +$part1size\0" \
777"format2=protect off $part2base +$part2size; " \
778 "erase $part2base +$part2size\0" \
779"format3=protect off $part3base +$part3size; " \
780 "erase $part3base +$part3size\0" \
781"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
782"kerneladdr=0x01100000\0" \
783"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
784"kernelfile=uImage\0" \
785"loadaddr=0x01000000\0" \
786"mbr=uCP1020.mbr\0" \
787"mbr_offset=0x00000000\0" \
788"netdev=eth0\0" \
789"nor_ubootaddr0=0xEC000000\0" \
790"nor_ubootaddr1=0xEFF80000\0" \
791"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
792 "run norkernelload; " \
793 "bootm $kerneladdr - $dtbaddr\0" \
794"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
795 "setenv cramfsaddr $part0base; " \
796 "cramfsload $dtbaddr $dtbfile; " \
797 "cramfsload $kerneladdr $kernelfile\0" \
798"part0base=0xEC100000\0" \
799"part0size=0x00700000\0" \
800"part1base=0xEC800000\0" \
801"part1size=0x02000000\0" \
802"part2base=0xEE800000\0" \
803"part2size=0x00800000\0" \
804"part3base=0xEF000000\0" \
805"part3size=0x00F80000\0" \
806"partENVbase=0xEC080000\0" \
807"partENVsize=0x00080000\0" \
808"program0=tftp part0-000000.bin; " \
809 "protect off $part0base +$filesize; " \
810 "erase $part0base +$filesize; " \
811 "cp.b $loadaddr $part0base $filesize; " \
812 "echo Verifying...; " \
813 "cmp.b $loadaddr $part0base $filesize\0" \
814"program1=tftp part1-000000.bin; " \
815 "protect off $part1base +$filesize; " \
816 "erase $part1base +$filesize; " \
817 "cp.b $loadaddr $part1base $filesize; " \
818 "echo Verifying...; " \
819 "cmp.b $loadaddr $part1base $filesize\0" \
820"program2=tftp part2-000000.bin; " \
821 "protect off $part2base +$filesize; " \
822 "erase $part2base +$filesize; " \
823 "cp.b $loadaddr $part2base $filesize; " \
824 "echo Verifying...; " \
825 "cmp.b $loadaddr $part2base $filesize\0" \
826"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
827 " console=$consoledev,$baudrate $othbootargs; " \
828 "tftp $rootfsaddr $rootfsfile; " \
829 "tftp $loadaddr $kernelfile; " \
830 "tftp $dtbaddr $dtbfile; " \
831 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
832"ramdisk_size=120000\0" \
833"ramdiskfile=rootfs.ext2.gz.uboot\0" \
834"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
835 "mw.l 0xffe0f008 0x00400000\0" \
836"rootfsaddr=0x02F00000\0" \
837"rootfsfile=rootfs.ext2.gz.uboot\0" \
838"rootpath=/opt/nfsroot\0" \
839"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
840 "sf probe 0; sf erase 0 +$filesize; " \
841 "sf write $loadaddr 0 $filesize\0" \
842"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
843 "protect off 0xeC000000 +$filesize; " \
844 "erase 0xEC000000 +$filesize; " \
845 "cp.b $loadaddr 0xEC000000 $filesize; " \
846 "cmp.b $loadaddr 0xEC000000 $filesize; " \
847 "protect on 0xeC000000 +$filesize\0" \
848"tftpflash=tftpboot $loadaddr $uboot; " \
849 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
850 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
851 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
852 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
853 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
854"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
855"ubootfile=u-boot.bin\0" \
856"upgrade=run flashuboot\0" \
857"usb_phy_type=ulpi\0 " \
858"boot_nfs= " \
859 "setenv bootargs root=/dev/nfs rw " \
860 "nfsroot=$serverip:$rootpath " \
861 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
862 "console=$consoledev,$baudrate $othbootargs;" \
863 "tftp $loadaddr $bootfile;" \
864 "tftp $fdtaddr $fdtfile;" \
865 "bootm $loadaddr - $fdtaddr\0" \
866"boot_hd = " \
867 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "usb start;" \
870 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
871 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
872 "bootm $loadaddr - $fdtaddr\0" \
873"boot_usb_fat = " \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs " \
876 "ramdisk_size=$ramdisk_size;" \
877 "usb start;" \
878 "fatload usb 0:2 $loadaddr $bootfile;" \
879 "fatload usb 0:2 $fdtaddr $fdtfile;" \
880 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
881 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
882"boot_usb_ext2 = " \
883 "setenv bootargs root=/dev/ram rw " \
884 "console=$consoledev,$baudrate $othbootargs " \
885 "ramdisk_size=$ramdisk_size;" \
886 "usb start;" \
887 "ext2load usb 0:4 $loadaddr $bootfile;" \
888 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
889 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
890 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
891"boot_nor = " \
892 "setenv bootargs root=/dev/$jffs2nor rw " \
893 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
894 "bootm $norbootaddr - $norfdtaddr\0 " \
895"boot_ram = " \
896 "setenv bootargs root=/dev/ram rw " \
897 "console=$consoledev,$baudrate $othbootargs " \
898 "ramdisk_size=$ramdisk_size;" \
899 "tftp $ramdiskaddr $ramdiskfile;" \
900 "tftp $loadaddr $bootfile;" \
901 "tftp $fdtaddr $fdtfile;" \
902 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
903
904#endif
905#endif
906
907#endif /* __CONFIG_H */