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Dave Liub19ecd32007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liub19ecd32007-09-18 12:37:57 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Dave Liub19ecd32007-09-18 12:37:57 +080011/*
12 * High Level Configuration Options
13 */
14#define CONFIG_E300 1 /* E300 family */
Peter Tyser72f2d392009-05-22 17:23:25 -050015#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liub19ecd32007-09-18 12:37:57 +080016#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
17
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020018#define CONFIG_SYS_TEXT_BASE 0xFE000000
19
Dave Liub19ecd32007-09-18 12:37:57 +080020/*
21 * System Clock Setup
22 */
23#ifdef CONFIG_PCISLAVE
24#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
25#else
26#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
27#endif
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ 66000000
31#endif
32
33/*
34 * Hardware Reset Configuration Word
35 * if CLKIN is 66MHz, then
36 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
37 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038#define CONFIG_SYS_HRCW_LOW (\
Dave Liub19ecd32007-09-18 12:37:57 +080039 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_1X1 |\
41 HRCWL_SVCOD_DIV_2 |\
42 HRCWL_CSB_TO_CLKIN_6X1 |\
43 HRCWL_CORE_TO_CSB_1_5X1)
44
45#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_HRCW_HIGH (\
Dave Liub19ecd32007-09-18 12:37:57 +080047 HRCWH_PCI_AGENT |\
48 HRCWH_PCI1_ARBITER_DISABLE |\
49 HRCWH_CORE_ENABLE |\
50 HRCWH_FROM_0XFFF00100 |\
51 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
53 HRCWH_ROM_LOC_LOCAL_16BIT |\
54 HRCWH_RL_EXT_LEGACY |\
55 HRCWH_TSEC1M_IN_RGMII |\
56 HRCWH_TSEC2M_IN_RGMII |\
57 HRCWH_BIG_ENDIAN |\
58 HRCWH_LDP_CLEAR)
59#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_HRCW_HIGH (\
Dave Liub19ecd32007-09-18 12:37:57 +080061 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0X00000100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#endif
74
Dave Liued5a0982008-03-04 16:59:22 +080075/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger0f193402011-10-11 23:57:18 -050077#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liued5a0982008-03-04 16:59:22 +080078
79/* System Priority Control Register */
Joe Hershberger0f193402011-10-11 23:57:18 -050080#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liued5a0982008-03-04 16:59:22 +080081
Dave Liub19ecd32007-09-18 12:37:57 +080082/*
Dave Liued5a0982008-03-04 16:59:22 +080083 * IP blocks clock configuration
Dave Liub19ecd32007-09-18 12:37:57 +080084 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
86#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
Joe Hershberger0f193402011-10-11 23:57:18 -050087#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liub19ecd32007-09-18 12:37:57 +080088
89/*
90 * System IO Config
91 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_SICRH 0x00000000
93#define CONFIG_SYS_SICRL 0x00000000
Dave Liub19ecd32007-09-18 12:37:57 +080094
95/*
96 * Output Buffer Impedance
97 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_OBIR 0x31100000
Dave Liub19ecd32007-09-18 12:37:57 +080099
Dave Liub19ecd32007-09-18 12:37:57 +0800100#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsov5cd61522009-06-10 00:25:31 +0400101#define CONFIG_HWCONFIG
Dave Liub19ecd32007-09-18 12:37:57 +0800102
103/*
104 * IMMR new address
105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_IMMR 0xE0000000
Dave Liub19ecd32007-09-18 12:37:57 +0800107
108/*
109 * DDR Setup
110 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
113#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
114#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
115#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershbergercc03b802011-10-11 23:57:29 -0500116#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
117 | DDRCDR_ODT \
118 | DDRCDR_Q_DRN)
119 /* 0x80080001 */ /* ODT 150ohm on SoC */
Dave Liub19ecd32007-09-18 12:37:57 +0800120
121#undef CONFIG_DDR_ECC /* support DDR ECC function */
122#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
123
124#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
125#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
126
127#if defined(CONFIG_SPD_EEPROM)
128#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
129#else
130/*
131 * Manually set up DDR parameters
Dave Liu925c8c82008-01-10 23:07:23 +0800132 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liub19ecd32007-09-18 12:37:57 +0800133 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
134 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_DDR_SIZE 512 /* MB */
136#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
Joe Hershberger0f193402011-10-11 23:57:18 -0500137#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500138 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
139 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
140 | CSCONFIG_ROW_BIT_14 \
141 | CSCONFIG_COL_BIT_10)
142 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger0f193402011-10-11 23:57:18 -0500144#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
145 | (0 << TIMING_CFG0_WRT_SHIFT) \
146 | (0 << TIMING_CFG0_RRT_SHIFT) \
147 | (0 << TIMING_CFG0_WWT_SHIFT) \
148 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
149 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
150 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
151 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liub19ecd32007-09-18 12:37:57 +0800152 /* 0x00620802 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500153#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
154 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
155 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
156 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
157 | (13 << TIMING_CFG1_REFREC_SHIFT) \
158 | (3 << TIMING_CFG1_WRREC_SHIFT) \
159 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
160 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Dave Liub19ecd32007-09-18 12:37:57 +0800161 /* 0x3935d322 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500162#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
163 | (6 << TIMING_CFG2_CPO_SHIFT) \
164 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
165 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
166 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
167 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
168 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
Dave Liu925c8c82008-01-10 23:07:23 +0800169 /* 0x131088c8 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500170#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
171 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liub19ecd32007-09-18 12:37:57 +0800172 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
174#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Joe Hershberger0f193402011-10-11 23:57:18 -0500175#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
176 | (0x1432 << SDRAM_MODE_SD_SHIFT))
Dave Liu925c8c82008-01-10 23:07:23 +0800177 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger0f193402011-10-11 23:57:18 -0500178#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liub19ecd32007-09-18 12:37:57 +0800179#endif
180
181/*
182 * Memory test
183 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
185#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
186#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liub19ecd32007-09-18 12:37:57 +0800187
188/*
189 * The reserved memory
190 */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liub19ecd32007-09-18 12:37:57 +0800192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
194#define CONFIG_SYS_RAMBOOT
Dave Liub19ecd32007-09-18 12:37:57 +0800195#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#undef CONFIG_SYS_RAMBOOT
Dave Liub19ecd32007-09-18 12:37:57 +0800197#endif
198
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao349a0152016-07-08 11:25:14 +0800200#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershberger0f193402011-10-11 23:57:18 -0500201#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liub19ecd32007-09-18 12:37:57 +0800202
203/*
204 * Initial RAM Base Address Setup
205 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_INIT_RAM_LOCK 1
207#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200208#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger0f193402011-10-11 23:57:18 -0500209#define CONFIG_SYS_GBL_DATA_OFFSET \
210 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liub19ecd32007-09-18 12:37:57 +0800211
212/*
213 * Local Bus Configuration & Clock Setup
214 */
Kim Phillips328040a2009-09-25 18:19:44 -0500215#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
216#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Brucedfe6e232010-06-17 11:37:18 -0500218#define CONFIG_FSL_ELBC 1
Dave Liub19ecd32007-09-18 12:37:57 +0800219
220/*
221 * FLASH on the Local Bus
222 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500223#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200224#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger0f193402011-10-11 23:57:18 -0500225#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
226#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
227#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liub19ecd32007-09-18 12:37:57 +0800228
Joe Hershberger0f193402011-10-11 23:57:18 -0500229 /* Window base at flash base */
230#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500231#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liub19ecd32007-09-18 12:37:57 +0800232
Joe Hershberger0f193402011-10-11 23:57:18 -0500233#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500234 | BR_PS_16 /* 16 bit port */ \
235 | BR_MS_GPCM /* MSEL = GPCM */ \
236 | BR_V) /* valid */
237#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Dave Liu723dff92008-01-10 23:08:26 +0800238 | OR_UPM_XAM \
239 | OR_GPCM_CSNT \
Anton Vorontsova6c0c072008-05-29 18:14:56 +0400240 | OR_GPCM_ACS_DIV2 \
Dave Liu723dff92008-01-10 23:08:26 +0800241 | OR_GPCM_XACS \
242 | OR_GPCM_SCY_15 \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500243 | OR_GPCM_TRLX_SET \
244 | OR_GPCM_EHTR_SET \
Joe Hershberger0f193402011-10-11 23:57:18 -0500245 | OR_GPCM_EAD)
Dave Liu723dff92008-01-10 23:08:26 +0800246 /* 0xFE000FF7 */
Dave Liub19ecd32007-09-18 12:37:57 +0800247
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
249#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liub19ecd32007-09-18 12:37:57 +0800250
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#undef CONFIG_SYS_FLASH_CHECKSUM
252#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
253#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liub19ecd32007-09-18 12:37:57 +0800254
255/*
256 * BCSR on the Local Bus
257 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_BCSR 0xF8000000
Joe Hershberger0f193402011-10-11 23:57:18 -0500259 /* Access window base at BCSR base */
260#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500261#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liub19ecd32007-09-18 12:37:57 +0800262
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500263#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
264 | BR_PS_8 \
265 | BR_MS_GPCM \
266 | BR_V)
267 /* 0xF8000801 */
268#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
269 | OR_GPCM_XAM \
270 | OR_GPCM_CSNT \
271 | OR_GPCM_XACS \
272 | OR_GPCM_SCY_15 \
273 | OR_GPCM_TRLX_SET \
274 | OR_GPCM_EHTR_SET \
275 | OR_GPCM_EAD)
276 /* 0xFFFFE9F7 */
Dave Liub19ecd32007-09-18 12:37:57 +0800277
278/*
279 * NAND Flash on the Local Bus
280 */
Anton Vorontsovc7538792008-10-08 20:52:54 +0400281#define CONFIG_CMD_NAND 1
Anton Vorontsovc7538792008-10-08 20:52:54 +0400282#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger0f193402011-10-11 23:57:18 -0500283#define CONFIG_NAND_FSL_ELBC 1
Anton Vorontsovc7538792008-10-08 20:52:54 +0400284
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500285#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger0f193402011-10-11 23:57:18 -0500286#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500287 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger0f193402011-10-11 23:57:18 -0500288 | BR_PS_8 /* 8 bit port */ \
Dave Liub19ecd32007-09-18 12:37:57 +0800289 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500290 | BR_V) /* valid */
291#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
Anton Vorontsovc7538792008-10-08 20:52:54 +0400292 | OR_FCM_BCTLD \
Dave Liub19ecd32007-09-18 12:37:57 +0800293 | OR_FCM_CST \
294 | OR_FCM_CHT \
295 | OR_FCM_SCY_1 \
Anton Vorontsovc7538792008-10-08 20:52:54 +0400296 | OR_FCM_RST \
Dave Liub19ecd32007-09-18 12:37:57 +0800297 | OR_FCM_TRLX \
Joe Hershberger0f193402011-10-11 23:57:18 -0500298 | OR_FCM_EHTR)
Anton Vorontsovc7538792008-10-08 20:52:54 +0400299 /* 0xFFFF919E */
Dave Liub19ecd32007-09-18 12:37:57 +0800300
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500302#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liub19ecd32007-09-18 12:37:57 +0800303
304/*
305 * Serial Port
306 */
307#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_NS16550_SERIAL
309#define CONFIG_SYS_NS16550_REG_SIZE 1
310#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liub19ecd32007-09-18 12:37:57 +0800311
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger0f193402011-10-11 23:57:18 -0500313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liub19ecd32007-09-18 12:37:57 +0800314
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200315#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
316#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liub19ecd32007-09-18 12:37:57 +0800317
Dave Liub19ecd32007-09-18 12:37:57 +0800318/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200319#define CONFIG_SYS_I2C
320#define CONFIG_SYS_I2C_FSL
321#define CONFIG_SYS_FSL_I2C_SPEED 400000
322#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
323#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
324#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liub19ecd32007-09-18 12:37:57 +0800325
326/*
327 * Config on-board RTC
328 */
329#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liub19ecd32007-09-18 12:37:57 +0800331
332/*
333 * General PCI
334 * Addresses are mapped 1-1.
335 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500336#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
337#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
338#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200339#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
340#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
341#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
342#define CONFIG_SYS_PCI_IO_BASE 0x00000000
343#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
344#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liub19ecd32007-09-18 12:37:57 +0800345
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
347#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
348#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liub19ecd32007-09-18 12:37:57 +0800349
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300350#define CONFIG_SYS_PCIE1_BASE 0xA0000000
351#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
352#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
353#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
354#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
355#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
356#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
357#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
358#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
359
360#define CONFIG_SYS_PCIE2_BASE 0xC0000000
361#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
362#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
363#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
364#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
365#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
366#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
367#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
368#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
369
Dave Liub19ecd32007-09-18 12:37:57 +0800370#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000371#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsov30c69922008-10-02 19:17:33 +0400372#ifndef __ASSEMBLY__
373extern int board_pci_host_broken(void);
374#endif
Kim Phillipsf1384292009-07-23 14:09:38 -0500375#define CONFIG_PCIE
Dave Liub19ecd32007-09-18 12:37:57 +0800376#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
377
Anton Vorontsov504867a2008-10-14 22:58:53 +0400378#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
Nikhil Badolac4cff522014-10-20 16:31:01 +0530379#define CONFIG_USB_EHCI_FSL
380#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov504867a2008-10-14 22:58:53 +0400381
Dave Liub19ecd32007-09-18 12:37:57 +0800382#undef CONFIG_EEPRO100
383#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200384#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liub19ecd32007-09-18 12:37:57 +0800385#endif /* CONFIG_PCI */
386
Dave Liub19ecd32007-09-18 12:37:57 +0800387/*
388 * TSEC
389 */
390#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200391#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger0f193402011-10-11 23:57:18 -0500392#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger0f193402011-10-11 23:57:18 -0500394#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liub19ecd32007-09-18 12:37:57 +0800395
396/*
397 * TSEC ethernet configuration
398 */
399#define CONFIG_MII 1 /* MII PHY management */
400#define CONFIG_TSEC1 1
401#define CONFIG_TSEC1_NAME "eTSEC0"
402#define CONFIG_TSEC2 1
403#define CONFIG_TSEC2_NAME "eTSEC1"
404#define TSEC1_PHY_ADDR 2
405#define TSEC2_PHY_ADDR 3
Anton Vorontsov32b1b702008-10-02 18:32:25 +0400406#define TSEC1_PHY_ADDR_SGMII 8
407#define TSEC2_PHY_ADDR_SGMII 4
Dave Liub19ecd32007-09-18 12:37:57 +0800408#define TSEC1_PHYIDX 0
409#define TSEC2_PHYIDX 0
410#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
411#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412
413/* Options are: TSEC[0-1] */
414#define CONFIG_ETHPRIME "eTSEC1"
415
Dave Liub8dc5872008-03-26 22:56:36 +0800416/* SERDES */
417#define CONFIG_FSL_SERDES
418#define CONFIG_FSL_SERDES1 0xe3000
419#define CONFIG_FSL_SERDES2 0xe3100
420
Dave Liub19ecd32007-09-18 12:37:57 +0800421/*
Dave Liu4056d7a2008-03-26 22:57:19 +0800422 * SATA
423 */
424#define CONFIG_LIBATA
425#define CONFIG_FSL_SATA
426
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200427#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu4056d7a2008-03-26 22:57:19 +0800428#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200429#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger0f193402011-10-11 23:57:18 -0500430#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
431#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu4056d7a2008-03-26 22:57:19 +0800432#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200433#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger0f193402011-10-11 23:57:18 -0500434#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
435#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu4056d7a2008-03-26 22:57:19 +0800436
437#ifdef CONFIG_FSL_SATA
438#define CONFIG_LBA48
Dave Liu4056d7a2008-03-26 22:57:19 +0800439#endif
440
441/*
Dave Liub19ecd32007-09-18 12:37:57 +0800442 * Environment
443 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200444#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200445 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger0f193402011-10-11 23:57:18 -0500446 #define CONFIG_ENV_ADDR \
447 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200448 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
449 #define CONFIG_ENV_SIZE 0x2000
Dave Liub19ecd32007-09-18 12:37:57 +0800450#else
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200451 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200453 #define CONFIG_ENV_SIZE 0x2000
Dave Liub19ecd32007-09-18 12:37:57 +0800454#endif
455
456#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200457#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liub19ecd32007-09-18 12:37:57 +0800458
459/*
460 * BOOTP options
461 */
462#define CONFIG_BOOTP_BOOTFILESIZE
463#define CONFIG_BOOTP_BOOTPATH
464#define CONFIG_BOOTP_GATEWAY
465#define CONFIG_BOOTP_HOSTNAME
466
Dave Liub19ecd32007-09-18 12:37:57 +0800467/*
468 * Command line configuration.
469 */
Dave Liub19ecd32007-09-18 12:37:57 +0800470
471#if defined(CONFIG_PCI)
472 #define CONFIG_CMD_PCI
473#endif
474
Dave Liub19ecd32007-09-18 12:37:57 +0800475#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips26c16d82010-04-15 17:36:05 -0500476#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liub19ecd32007-09-18 12:37:57 +0800477
478#undef CONFIG_WATCHDOG /* watchdog disabled */
479
Andy Fleming1463b4b2008-10-30 16:50:14 -0500480#ifdef CONFIG_MMC
481#define CONFIG_FSL_ESDHC
Chenhui Zhao025eab02011-01-04 17:23:05 +0800482#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleming1463b4b2008-10-30 16:50:14 -0500483#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Andy Fleming1463b4b2008-10-30 16:50:14 -0500484#endif
485
Dave Liub19ecd32007-09-18 12:37:57 +0800486/*
487 * Miscellaneous configurable options
488 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200489#define CONFIG_SYS_LONGHELP /* undef to save memory */
490#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liub19ecd32007-09-18 12:37:57 +0800491
492#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200493 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liub19ecd32007-09-18 12:37:57 +0800494#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200495 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liub19ecd32007-09-18 12:37:57 +0800496#endif
497
Joe Hershberger0f193402011-10-11 23:57:18 -0500498 /* Print Buffer Size */
499#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
500#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
501 /* Boot Argument Buffer Size */
502#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liub19ecd32007-09-18 12:37:57 +0800503
504/*
505 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700506 * have to be in the first 256 MB of memory, since this is
Dave Liub19ecd32007-09-18 12:37:57 +0800507 * the maximum mapped by the Linux kernel during initialization.
508 */
Joe Hershberger0f193402011-10-11 23:57:18 -0500509#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kevin Hao9c747962016-07-08 11:25:15 +0800510#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Dave Liub19ecd32007-09-18 12:37:57 +0800511
512/*
513 * Core HID Setup
514 */
Kim Phillipsf3c7cd92010-04-20 19:37:54 -0500515#define CONFIG_SYS_HID0_INIT 0x000000000
516#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
517 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200518#define CONFIG_SYS_HID2 HID2_HBE
Dave Liub19ecd32007-09-18 12:37:57 +0800519
520/*
Dave Liub19ecd32007-09-18 12:37:57 +0800521 * MMU Setup
522 */
Becky Bruce03ea1be2008-05-08 19:02:12 -0500523#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liub19ecd32007-09-18 12:37:57 +0800524
525/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200526#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
527#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liub19ecd32007-09-18 12:37:57 +0800528
Joe Hershberger0f193402011-10-11 23:57:18 -0500529#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500530 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500531 | BATL_MEMCOHERENCE)
532#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
533 | BATU_BL_256M \
534 | BATU_VS \
535 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200536#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
537#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liub19ecd32007-09-18 12:37:57 +0800538
Joe Hershberger0f193402011-10-11 23:57:18 -0500539#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500540 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500541 | BATL_MEMCOHERENCE)
542#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
543 | BATU_BL_256M \
544 | BATU_VS \
545 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200546#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
547#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liub19ecd32007-09-18 12:37:57 +0800548
549/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger0f193402011-10-11 23:57:18 -0500550#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500551 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500552 | BATL_CACHEINHIBIT \
553 | BATL_GUARDEDSTORAGE)
554#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
555 | BATU_BL_8M \
556 | BATU_VS \
557 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200558#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
559#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liub19ecd32007-09-18 12:37:57 +0800560
561/* BCSR: cache-inhibit and guarded */
Joe Hershberger0f193402011-10-11 23:57:18 -0500562#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500563 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500564 | BATL_CACHEINHIBIT \
565 | BATL_GUARDEDSTORAGE)
566#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
567 | BATU_BL_128K \
568 | BATU_VS \
569 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200570#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
571#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liub19ecd32007-09-18 12:37:57 +0800572
573/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger0f193402011-10-11 23:57:18 -0500574#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500575 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500576 | BATL_MEMCOHERENCE)
577#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
578 | BATU_BL_32M \
579 | BATU_VS \
580 | BATU_VP)
581#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500582 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500583 | BATL_CACHEINHIBIT \
584 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200585#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liub19ecd32007-09-18 12:37:57 +0800586
587/* Stack in dcache: cacheable, no memory coherence */
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500588#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger0f193402011-10-11 23:57:18 -0500589#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
590 | BATU_BL_128K \
591 | BATU_VS \
592 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200593#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
594#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liub19ecd32007-09-18 12:37:57 +0800595
596#ifdef CONFIG_PCI
597/* PCI MEM space: cacheable */
Joe Hershberger0f193402011-10-11 23:57:18 -0500598#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500599 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500600 | BATL_MEMCOHERENCE)
601#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200605#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
606#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liub19ecd32007-09-18 12:37:57 +0800607/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger0f193402011-10-11 23:57:18 -0500608#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500609 | BATL_PP_RW \
Joe Hershberger0f193402011-10-11 23:57:18 -0500610 | BATL_CACHEINHIBIT \
611 | BATL_GUARDEDSTORAGE)
612#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
613 | BATU_BL_256M \
614 | BATU_VS \
615 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200616#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
617#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liub19ecd32007-09-18 12:37:57 +0800618#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200619#define CONFIG_SYS_IBAT6L (0)
620#define CONFIG_SYS_IBAT6U (0)
621#define CONFIG_SYS_IBAT7L (0)
622#define CONFIG_SYS_IBAT7U (0)
623#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
624#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
625#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
626#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liub19ecd32007-09-18 12:37:57 +0800627#endif
628
Dave Liub19ecd32007-09-18 12:37:57 +0800629#if defined(CONFIG_CMD_KGDB)
630#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liub19ecd32007-09-18 12:37:57 +0800631#endif
632
633/*
634 * Environment Configuration
635 */
636
637#define CONFIG_ENV_OVERWRITE
638
639#if defined(CONFIG_TSEC_ENET)
640#define CONFIG_HAS_ETH0
Dave Liub19ecd32007-09-18 12:37:57 +0800641#define CONFIG_HAS_ETH1
Dave Liub19ecd32007-09-18 12:37:57 +0800642#endif
643
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500644#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liub19ecd32007-09-18 12:37:57 +0800645
Dave Liub19ecd32007-09-18 12:37:57 +0800646#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
647
648#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger0f193402011-10-11 23:57:18 -0500649 "netdev=eth0\0" \
650 "consoledev=ttyS0\0" \
651 "ramdiskaddr=1000000\0" \
652 "ramdiskfile=ramfs.83xx\0" \
653 "fdtaddr=780000\0" \
654 "fdtfile=mpc8379_mds.dtb\0" \
655 ""
Dave Liub19ecd32007-09-18 12:37:57 +0800656
657#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger0f193402011-10-11 23:57:18 -0500658 "setenv bootargs root=/dev/nfs rw " \
659 "nfsroot=$serverip:$rootpath " \
660 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
661 "$netdev:off " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr - $fdtaddr"
Dave Liub19ecd32007-09-18 12:37:57 +0800666
667#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger0f193402011-10-11 23:57:18 -0500668 "setenv bootargs root=/dev/ram rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $ramdiskaddr $ramdiskfile;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liub19ecd32007-09-18 12:37:57 +0800674
Dave Liub19ecd32007-09-18 12:37:57 +0800675#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
676
677#endif /* __CONFIG_H */