blob: 5f4d9d822495340ca3bd391c4bb16c0a03ee5943 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kever Yang5f948962017-06-23 17:17:50 +08002/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
Kever Yang5f948962017-06-23 17:17:50 +08004 */
5#ifndef _ASM_ARCH_GRF_RK322X_H
6#define _ASM_ARCH_GRF_RK322X_H
7
Kever Yang5f948962017-06-23 17:17:50 +08008struct rk322x_grf {
9 unsigned int gpio0a_iomux;
10 unsigned int gpio0b_iomux;
11 unsigned int gpio0c_iomux;
12 unsigned int gpio0d_iomux;
13
14 unsigned int gpio1a_iomux;
15 unsigned int gpio1b_iomux;
16 unsigned int gpio1c_iomux;
17 unsigned int gpio1d_iomux;
18
19 unsigned int gpio2a_iomux;
20 unsigned int gpio2b_iomux;
21 unsigned int gpio2c_iomux;
22 unsigned int gpio2d_iomux;
23
24 unsigned int gpio3a_iomux;
25 unsigned int gpio3b_iomux;
26 unsigned int gpio3c_iomux;
27 unsigned int gpio3d_iomux;
28
29 unsigned int reserved1[4];
30 unsigned int con_iomux;
31 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
32 unsigned int gpio0_p[4];
33 unsigned int gpio1_p[4];
34 unsigned int gpio2_p[4];
35 unsigned int gpio3_p[4];
36 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
37 unsigned int gpio0_e[4];
38 unsigned int gpio1_e[4];
39 unsigned int gpio2_e[4];
40 unsigned int gpio3_e[4];
41 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
42 unsigned int soc_con[7];
43 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
44 unsigned int soc_status[3];
45 unsigned int chip_id;
46 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
47 unsigned int cpu_con[4];
48 unsigned int reserved7[4];
49 unsigned int cpu_status[2];
50 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
51 unsigned int os_reg[8];
52 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
53 unsigned int ddrc_stat;
David Wud0f8d782017-08-14 15:04:28 +080054 unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
55 unsigned int sig_detect_con[2];
56 unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
57 unsigned int sig_detect_status[2];
58 unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
59 unsigned int sig_detect_clr[2];
60 unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
61 unsigned int emmc_det;
62 unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
63 unsigned int host0_con[3];
64 unsigned int reserved15;
65 unsigned int host1_con[3];
66 unsigned int reserved16;
67 unsigned int host2_con[3];
68 unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
69 unsigned int usbphy0_con[27];
70 unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
71 unsigned int usbphy1_con[27];
72 unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
73 unsigned int otg_con0;
74 unsigned int uoc_status0;
75 unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
76 unsigned int mac_con[2];
77 unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
78 unsigned int macphy_con[4];
79 unsigned int macphy_status;
Kever Yang5f948962017-06-23 17:17:50 +080080};
81check_member(rk322x_grf, ddrc_stat, 0x604);
82
83struct rk322x_sgrf {
84 unsigned int soc_con[11];
85 unsigned int busdmac_con[4];
86};
87
David Wud0f8d782017-08-14 15:04:28 +080088/* GRF_MACPHY_CON0 */
89enum {
90 MACPHY_CFG_ENABLE_SHIFT = 0,
91 MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,
92};
Kever Yang5f948962017-06-23 17:17:50 +080093#endif