Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Renesas RCar Gen3 RPC QSPI driver |
| 4 | * |
| 5 | * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | #include <clk.h> |
| 12 | #include <dm.h> |
| 13 | #include <dm/of_access.h> |
| 14 | #include <dt-structs.h> |
| 15 | #include <errno.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Simon Glass | c06c1be | 2020-05-10 11:40:08 -0600 | [diff] [blame] | 17 | #include <linux/bug.h> |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 18 | #include <linux/errno.h> |
| 19 | #include <spi.h> |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 20 | #include <spi-mem.h> |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 21 | #include <wait_bit.h> |
| 22 | |
| 23 | #define RPC_CMNCR 0x0000 /* R/W */ |
| 24 | #define RPC_CMNCR_MD BIT(31) |
| 25 | #define RPC_CMNCR_SFDE BIT(24) |
| 26 | #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) |
| 27 | #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) |
| 28 | #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) |
| 29 | #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) |
| 30 | #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ |
| 31 | RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) |
| 32 | #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) |
| 33 | #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) |
| 34 | #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) |
| 35 | #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ |
| 36 | RPC_CMNCR_IO3FV(3)) |
| 37 | #define RPC_CMNCR_CPHAT BIT(6) |
| 38 | #define RPC_CMNCR_CPHAR BIT(5) |
| 39 | #define RPC_CMNCR_SSLP BIT(4) |
| 40 | #define RPC_CMNCR_CPOL BIT(3) |
| 41 | #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) |
| 42 | |
| 43 | #define RPC_SSLDR 0x0004 /* R/W */ |
| 44 | #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) |
| 45 | #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) |
| 46 | #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) |
| 47 | |
| 48 | #define RPC_DRCR 0x000C /* R/W */ |
| 49 | #define RPC_DRCR_SSLN BIT(24) |
| 50 | #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) |
| 51 | #define RPC_DRCR_RCF BIT(9) |
| 52 | #define RPC_DRCR_RBE BIT(8) |
| 53 | #define RPC_DRCR_SSLE BIT(0) |
| 54 | |
| 55 | #define RPC_DRCMR 0x0010 /* R/W */ |
| 56 | #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) |
| 57 | #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) |
| 58 | |
| 59 | #define RPC_DREAR 0x0014 /* R/W */ |
| 60 | #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) |
| 61 | #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) |
| 62 | |
| 63 | #define RPC_DROPR 0x0018 /* R/W */ |
| 64 | #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) |
| 65 | #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) |
| 66 | #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) |
| 67 | #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) |
| 68 | |
| 69 | #define RPC_DRENR 0x001C /* R/W */ |
| 70 | #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) |
| 71 | #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) |
| 72 | #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) |
| 73 | #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) |
| 74 | #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) |
| 75 | #define RPC_DRENR_DME BIT(15) |
| 76 | #define RPC_DRENR_CDE BIT(14) |
| 77 | #define RPC_DRENR_OCDE BIT(12) |
| 78 | #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) |
| 79 | #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) |
| 80 | |
| 81 | #define RPC_SMCR 0x0020 /* R/W */ |
| 82 | #define RPC_SMCR_SSLKP BIT(8) |
| 83 | #define RPC_SMCR_SPIRE BIT(2) |
| 84 | #define RPC_SMCR_SPIWE BIT(1) |
| 85 | #define RPC_SMCR_SPIE BIT(0) |
| 86 | |
| 87 | #define RPC_SMCMR 0x0024 /* R/W */ |
| 88 | #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) |
| 89 | #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) |
| 90 | |
| 91 | #define RPC_SMADR 0x0028 /* R/W */ |
| 92 | #define RPC_SMOPR 0x002C /* R/W */ |
| 93 | #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) |
| 94 | #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) |
| 95 | #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) |
| 96 | #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) |
| 97 | |
| 98 | #define RPC_SMENR 0x0030 /* R/W */ |
| 99 | #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) |
| 100 | #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) |
| 101 | #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) |
| 102 | #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) |
| 103 | #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) |
| 104 | #define RPC_SMENR_DME BIT(15) |
| 105 | #define RPC_SMENR_CDE BIT(14) |
| 106 | #define RPC_SMENR_OCDE BIT(12) |
| 107 | #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) |
| 108 | #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) |
| 109 | #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) |
| 110 | |
| 111 | #define RPC_SMRDR0 0x0038 /* R */ |
| 112 | #define RPC_SMRDR1 0x003C /* R */ |
| 113 | #define RPC_SMWDR0 0x0040 /* R/W */ |
| 114 | #define RPC_SMWDR1 0x0044 /* R/W */ |
| 115 | #define RPC_CMNSR 0x0048 /* R */ |
| 116 | #define RPC_CMNSR_SSLF BIT(1) |
| 117 | #define RPC_CMNSR_TEND BIT(0) |
| 118 | |
| 119 | #define RPC_DRDMCR 0x0058 /* R/W */ |
| 120 | #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) |
| 121 | |
| 122 | #define RPC_DRDRENR 0x005C /* R/W */ |
| 123 | #define RPC_DRDRENR_HYPE (0x5 << 12) |
| 124 | #define RPC_DRDRENR_ADDRE BIT(8) |
| 125 | #define RPC_DRDRENR_OPDRE BIT(4) |
| 126 | #define RPC_DRDRENR_DRDRE BIT(0) |
| 127 | |
| 128 | #define RPC_SMDMCR 0x0060 /* R/W */ |
| 129 | #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) |
| 130 | |
| 131 | #define RPC_SMDRENR 0x0064 /* R/W */ |
| 132 | #define RPC_SMDRENR_HYPE (0x5 << 12) |
| 133 | #define RPC_SMDRENR_ADDRE BIT(8) |
| 134 | #define RPC_SMDRENR_OPDRE BIT(4) |
| 135 | #define RPC_SMDRENR_SPIDRE BIT(0) |
| 136 | |
| 137 | #define RPC_PHYCNT 0x007C /* R/W */ |
| 138 | #define RPC_PHYCNT_CAL BIT(31) |
| 139 | #define PRC_PHYCNT_OCTA_AA BIT(22) |
| 140 | #define PRC_PHYCNT_OCTA_SA BIT(23) |
| 141 | #define PRC_PHYCNT_EXDS BIT(21) |
| 142 | #define RPC_PHYCNT_OCT BIT(20) |
| 143 | #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) |
Hai Pham | 581d253 | 2021-08-05 14:38:26 +0700 | [diff] [blame] | 144 | #define RPC_PHYCNT_STRTIM2(v) ((((v) & 0x7) << 15) | (((v) & 0x8) << 24)) |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 145 | #define RPC_PHYCNT_WBUF2 BIT(4) |
| 146 | #define RPC_PHYCNT_WBUF BIT(2) |
| 147 | #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) |
| 148 | |
| 149 | #define RPC_PHYINT 0x0088 /* R/W */ |
| 150 | #define RPC_PHYINT_RSTEN BIT(18) |
| 151 | #define RPC_PHYINT_WPEN BIT(17) |
| 152 | #define RPC_PHYINT_INTEN BIT(16) |
| 153 | #define RPC_PHYINT_RST BIT(2) |
| 154 | #define RPC_PHYINT_WP BIT(1) |
| 155 | #define RPC_PHYINT_INT BIT(0) |
| 156 | |
| 157 | #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ |
| 158 | #define RPC_WBUF_SIZE 0x100 |
| 159 | |
| 160 | DECLARE_GLOBAL_DATA_PTR; |
| 161 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 162 | struct rpc_spi_plat { |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 163 | fdt_addr_t regs; |
| 164 | fdt_addr_t extr; |
| 165 | s32 freq; /* Default clock freq, -1 for none */ |
| 166 | }; |
| 167 | |
| 168 | struct rpc_spi_priv { |
| 169 | fdt_addr_t regs; |
| 170 | fdt_addr_t extr; |
| 171 | struct clk clk; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | static int rpc_spi_wait_sslf(struct udevice *dev) |
| 175 | { |
| 176 | struct rpc_spi_priv *priv = dev_get_priv(dev->parent); |
| 177 | |
| 178 | return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF, |
| 179 | false, 1000, false); |
| 180 | } |
| 181 | |
| 182 | static int rpc_spi_wait_tend(struct udevice *dev) |
| 183 | { |
| 184 | struct rpc_spi_priv *priv = dev_get_priv(dev->parent); |
| 185 | |
| 186 | return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND, |
| 187 | true, 1000, false); |
| 188 | } |
| 189 | |
| 190 | static void rpc_spi_flush_read_cache(struct udevice *dev) |
| 191 | { |
| 192 | struct udevice *bus = dev->parent; |
| 193 | struct rpc_spi_priv *priv = dev_get_priv(bus); |
| 194 | |
| 195 | /* Flush read cache */ |
| 196 | writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) | |
| 197 | RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE, |
| 198 | priv->regs + RPC_DRCR); |
| 199 | readl(priv->regs + RPC_DRCR); |
| 200 | |
| 201 | } |
| 202 | |
Hai Pham | 286ed07 | 2021-08-16 09:26:36 +0700 | [diff] [blame] | 203 | static u32 rpc_spi_get_strobe_delay(void) |
| 204 | { |
| 205 | #ifndef CONFIG_RZA1 |
| 206 | u32 cpu_type = rmobile_get_cpu_type(); |
| 207 | |
| 208 | /* |
| 209 | * NOTE: RPC_PHYCNT_STRTIM value: |
| 210 | * 0: On H3 ES1.x (not supported in mainline U-Boot) |
| 211 | * 6: On M3 ES1.x |
| 212 | * 7: On other R-Car Gen3 |
Hai Pham | 581d253 | 2021-08-05 14:38:26 +0700 | [diff] [blame] | 213 | * 15: On R-Car Gen4 |
Hai Pham | 286ed07 | 2021-08-16 09:26:36 +0700 | [diff] [blame] | 214 | */ |
| 215 | if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1) |
| 216 | return RPC_PHYCNT_STRTIM(6); |
Hai Pham | 581d253 | 2021-08-05 14:38:26 +0700 | [diff] [blame] | 217 | else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 || |
Hai Pham | 87336f0 | 2024-01-28 16:52:05 +0100 | [diff] [blame] | 218 | cpu_type == RMOBILE_CPU_TYPE_R8A779G0 || |
| 219 | cpu_type == RMOBILE_CPU_TYPE_R8A779H0) |
Hai Pham | 581d253 | 2021-08-05 14:38:26 +0700 | [diff] [blame] | 220 | return RPC_PHYCNT_STRTIM2(15); |
Hai Pham | 286ed07 | 2021-08-16 09:26:36 +0700 | [diff] [blame] | 221 | else |
| 222 | #endif |
| 223 | return RPC_PHYCNT_STRTIM(7); |
| 224 | } |
| 225 | |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 226 | static int rpc_spi_claim_bus(struct udevice *dev, bool manual) |
| 227 | { |
| 228 | struct udevice *bus = dev->parent; |
| 229 | struct rpc_spi_priv *priv = dev_get_priv(bus); |
| 230 | |
Hai Pham | 286ed07 | 2021-08-16 09:26:36 +0700 | [diff] [blame] | 231 | /* NOTE: The 0x260 are undocumented bits, but they must be set. */ |
| 232 | writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 233 | priv->regs + RPC_PHYCNT); |
| 234 | writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE | |
| 235 | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0), |
| 236 | priv->regs + RPC_CMNCR); |
| 237 | |
| 238 | writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) | |
| 239 | RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR); |
| 240 | |
| 241 | rpc_spi_flush_read_cache(dev); |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static int rpc_spi_release_bus(struct udevice *dev) |
| 247 | { |
| 248 | struct udevice *bus = dev->parent; |
| 249 | struct rpc_spi_priv *priv = dev_get_priv(bus); |
| 250 | |
| 251 | /* NOTE: The 0x260 are undocumented bits, but they must be set. */ |
Hai Pham | 286ed07 | 2021-08-16 09:26:36 +0700 | [diff] [blame] | 252 | writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 253 | |
| 254 | rpc_spi_flush_read_cache(dev); |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 259 | static int rpc_spi_mem_exec_op(struct spi_slave *spi, |
| 260 | const struct spi_mem_op *op) |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 261 | { |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 262 | struct udevice *bus = spi->dev->parent; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 263 | struct rpc_spi_priv *priv = dev_get_priv(bus); |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 264 | const void *dout = op->data.buf.out ? op->data.buf.out : NULL; |
| 265 | void *din = op->data.buf.in ? op->data.buf.in : NULL; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 266 | int ret = 0; |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 267 | u32 offset = 0; |
| 268 | u32 smenr, smcr; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 269 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 270 | smenr = 0; |
| 271 | offset = op->addr.val; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 272 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 273 | switch (op->data.dir) { |
| 274 | case SPI_MEM_DATA_IN: |
| 275 | rpc_spi_claim_bus(spi->dev, false); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 276 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 277 | writel(0, priv->regs + RPC_DRCMR); |
| 278 | writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); |
| 279 | smenr |= RPC_DRENR_CDE; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 280 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 281 | writel(0, priv->regs + RPC_DREAR); |
| 282 | if (op->addr.nbytes == 4) { |
| 283 | writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), |
| 284 | priv->regs + RPC_DREAR); |
| 285 | smenr |= RPC_DRENR_ADE(0xF); |
| 286 | } else if (op->addr.nbytes == 3) { |
| 287 | smenr |= RPC_DRENR_ADE(0x7); |
| 288 | } else { |
| 289 | smenr |= RPC_DRENR_ADE(0); |
| 290 | } |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 291 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 292 | writel(0, priv->regs + RPC_DRDMCR); |
| 293 | if (op->dummy.nbytes) { |
| 294 | writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); |
| 295 | smenr |= RPC_DRENR_DME; |
| 296 | } |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 297 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 298 | writel(0, priv->regs + RPC_DROPR); |
| 299 | writel(smenr, priv->regs + RPC_DRENR); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 300 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 301 | memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 302 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 303 | rpc_spi_release_bus(spi->dev); |
| 304 | break; |
| 305 | case SPI_MEM_DATA_OUT: |
| 306 | case SPI_MEM_NO_DATA: |
| 307 | rpc_spi_claim_bus(spi->dev, true); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 308 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 309 | writel(0, priv->regs + RPC_SMCR); |
| 310 | writel(0, priv->regs + RPC_SMCMR); |
| 311 | writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR); |
| 312 | smenr |= RPC_SMENR_CDE; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 313 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 314 | writel(0, priv->regs + RPC_SMADR); |
| 315 | if (op->addr.nbytes == 4) |
| 316 | smenr |= RPC_SMENR_ADE(0xF); |
| 317 | else if (op->addr.nbytes == 3) |
| 318 | smenr |= RPC_SMENR_ADE(0x7); |
| 319 | else |
| 320 | smenr |= RPC_SMENR_ADE(0); |
| 321 | writel(offset, priv->regs + RPC_SMADR); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 322 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 323 | writel(0, priv->regs + RPC_SMDMCR); |
| 324 | if (op->dummy.nbytes) { |
| 325 | writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_SMDMCR); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 326 | smenr |= RPC_SMENR_DME; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | writel(0, priv->regs + RPC_SMOPR); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 330 | writel(0, priv->regs + RPC_SMDRENR); |
| 331 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 332 | if (dout && op->data.nbytes) { |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 333 | u32 *datout = (u32 *)dout; |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 334 | u32 wloop = DIV_ROUND_UP(op->data.nbytes, 4); |
| 335 | |
| 336 | smenr |= RPC_SMENR_SPIDE(0xF); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 337 | |
| 338 | while (wloop--) { |
| 339 | smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE; |
| 340 | if (wloop >= 1) |
| 341 | smcr |= RPC_SMCR_SSLKP; |
| 342 | writel(smenr, priv->regs + RPC_SMENR); |
| 343 | writel(*datout, priv->regs + RPC_SMWDR0); |
| 344 | writel(smcr, priv->regs + RPC_SMCR); |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 345 | ret = rpc_spi_wait_tend(spi->dev); |
| 346 | if (ret) { |
| 347 | rpc_spi_release_bus(spi->dev); |
| 348 | return ret; |
| 349 | } |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 350 | datout++; |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 351 | smenr &= (~RPC_SMENR_CDE & ~RPC_SMENR_ADE(0xF)); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 352 | } |
| 353 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 354 | ret = rpc_spi_wait_sslf(spi->dev); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 355 | } else { |
| 356 | writel(smenr, priv->regs + RPC_SMENR); |
| 357 | writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR); |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 358 | ret = rpc_spi_wait_tend(spi->dev); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 359 | } |
| 360 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 361 | rpc_spi_release_bus(spi->dev); |
| 362 | break; |
| 363 | default: |
| 364 | break; |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 365 | } |
| 366 | |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 367 | return ret; |
| 368 | } |
| 369 | |
| 370 | static int rpc_spi_set_speed(struct udevice *bus, uint speed) |
| 371 | { |
| 372 | /* This is a SPI NOR controller, do nothing. */ |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static int rpc_spi_set_mode(struct udevice *bus, uint mode) |
| 377 | { |
| 378 | /* This is a SPI NOR controller, do nothing. */ |
| 379 | return 0; |
| 380 | } |
| 381 | |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 382 | static const struct spi_controller_mem_ops rpc_spi_mem_ops = { |
| 383 | .exec_op = rpc_spi_mem_exec_op |
| 384 | }; |
| 385 | |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 386 | static int rpc_spi_bind(struct udevice *parent) |
| 387 | { |
| 388 | const void *fdt = gd->fdt_blob; |
| 389 | ofnode node; |
| 390 | int ret, off; |
| 391 | |
| 392 | /* |
| 393 | * Check if there are any SPI NOR child nodes, if so, bind as |
| 394 | * this controller will be operated in SPI mode. |
| 395 | */ |
| 396 | dev_for_each_subnode(node, parent) { |
| 397 | off = ofnode_to_offset(node); |
| 398 | |
| 399 | ret = fdt_node_check_compatible(fdt, off, "spi-flash"); |
| 400 | if (!ret) |
| 401 | return 0; |
| 402 | |
| 403 | ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor"); |
| 404 | if (!ret) |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | return -ENODEV; |
| 409 | } |
| 410 | |
| 411 | static int rpc_spi_probe(struct udevice *dev) |
| 412 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 413 | struct rpc_spi_plat *plat = dev_get_plat(dev); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 414 | struct rpc_spi_priv *priv = dev_get_priv(dev); |
| 415 | |
| 416 | priv->regs = plat->regs; |
| 417 | priv->extr = plat->extr; |
Marek Vasut | f9db3b3 | 2019-05-04 18:52:33 +0200 | [diff] [blame] | 418 | #if CONFIG_IS_ENABLED(CLK) |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 419 | clk_enable(&priv->clk); |
Marek Vasut | f9db3b3 | 2019-05-04 18:52:33 +0200 | [diff] [blame] | 420 | #endif |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 421 | return 0; |
| 422 | } |
| 423 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 424 | static int rpc_spi_of_to_plat(struct udevice *bus) |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 425 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 426 | struct rpc_spi_plat *plat = dev_get_plat(bus); |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 427 | |
| 428 | plat->regs = dev_read_addr_index(bus, 0); |
| 429 | plat->extr = dev_read_addr_index(bus, 1); |
| 430 | |
Marek Vasut | f9db3b3 | 2019-05-04 18:52:33 +0200 | [diff] [blame] | 431 | #if CONFIG_IS_ENABLED(CLK) |
| 432 | struct rpc_spi_priv *priv = dev_get_priv(bus); |
| 433 | int ret; |
| 434 | |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 435 | ret = clk_get_by_index(bus, 0, &priv->clk); |
| 436 | if (ret < 0) { |
| 437 | printf("%s: Could not get clock for %s: %d\n", |
| 438 | __func__, bus->name, ret); |
| 439 | return ret; |
| 440 | } |
Marek Vasut | f9db3b3 | 2019-05-04 18:52:33 +0200 | [diff] [blame] | 441 | #endif |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 442 | |
| 443 | plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000); |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static const struct dm_spi_ops rpc_spi_ops = { |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 449 | .set_speed = rpc_spi_set_speed, |
| 450 | .set_mode = rpc_spi_set_mode, |
Cong Dang | ce33563 | 2022-08-25 06:06:54 +0700 | [diff] [blame] | 451 | .mem_ops = &rpc_spi_mem_ops |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 452 | }; |
| 453 | |
| 454 | static const struct udevice_id rpc_spi_ids[] = { |
Geert Uytterhoeven | 431ded6 | 2022-03-29 14:19:09 +0200 | [diff] [blame] | 455 | { .compatible = "renesas,r7s72100-rpc-if" }, |
| 456 | { .compatible = "renesas,rcar-gen3-rpc-if" }, |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 457 | { } |
| 458 | }; |
| 459 | |
| 460 | U_BOOT_DRIVER(rpc_spi) = { |
| 461 | .name = "rpc_spi", |
| 462 | .id = UCLASS_SPI, |
| 463 | .of_match = rpc_spi_ids, |
| 464 | .ops = &rpc_spi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 465 | .of_to_plat = rpc_spi_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 466 | .plat_auto = sizeof(struct rpc_spi_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 467 | .priv_auto = sizeof(struct rpc_spi_priv), |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 468 | .bind = rpc_spi_bind, |
| 469 | .probe = rpc_spi_probe, |
| 470 | }; |