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T Karthik Reddy501c2062021-08-10 06:50:18 -06001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Xilinx ZynqMP SOC driver
4 *
5 * Copyright (C) 2021 Xilinx, Inc.
Michal Simeka8c94362023-07-10 14:35:49 +02006 * Michal Simek <michal.simek@amd.com>
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +02007 *
8 * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
9 * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
T Karthik Reddy501c2062021-08-10 06:50:18 -060010 */
11
12#include <common.h>
13#include <dm.h>
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020014#include <dm/device_compat.h>
T Karthik Reddy501c2062021-08-10 06:50:18 -060015#include <asm/cache.h>
16#include <soc.h>
17#include <zynqmp_firmware.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/arch/hardware.h>
20
21/*
22 * Zynqmp has 4 silicon revisions
23 * v0 -> 0(XCZU9EG-ES1)
24 * v1 -> 1(XCZU3EG-ES1, XCZU15EG-ES1)
25 * v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1)
26 * v3 -> 3(Production Level)
27 */
28static const char zynqmp_family[] = "ZynqMP";
29
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020030#define EFUSE_VCU_DIS_SHIFT 8
31#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT)
32#define EFUSE_GPU_DIS_SHIFT 5
33#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT)
34#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0)
35#define IDCODE2_PL_INIT_SHIFT 9
36#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT)
37
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +053038#define ZYNQMP_VERSION_SIZE 10
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020039
40enum {
41 ZYNQMP_VARIANT_EG = BIT(0),
42 ZYNQMP_VARIANT_EV = BIT(1),
43 ZYNQMP_VARIANT_CG = BIT(2),
44 ZYNQMP_VARIANT_DR = BIT(3),
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +053045 ZYNQMP_VARIANT_DR_SE = BIT(4),
46 ZYNQMP_VARIANT_EG_SE = BIT(5),
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020047};
48
49struct zynqmp_device {
50 u32 id;
51 u8 device;
52 u8 variants;
53};
54
T Karthik Reddy501c2062021-08-10 06:50:18 -060055struct soc_xilinx_zynqmp_priv {
56 const char *family;
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020057 char machine[ZYNQMP_VERSION_SIZE];
T Karthik Reddy501c2062021-08-10 06:50:18 -060058 char revision;
59};
60
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020061static const struct zynqmp_device zynqmp_devices[] = {
62 {
63 .id = 0x04688093,
64 .device = 1,
65 .variants = ZYNQMP_VARIANT_EG,
66 },
67 {
68 .id = 0x04711093,
69 .device = 2,
70 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
71 },
72 {
73 .id = 0x04710093,
74 .device = 3,
75 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
76 },
77 {
78 .id = 0x04721093,
79 .device = 4,
80 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
81 ZYNQMP_VARIANT_EV,
82 },
83 {
84 .id = 0x04720093,
85 .device = 5,
86 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
87 ZYNQMP_VARIANT_EV,
88 },
89 {
90 .id = 0x04739093,
91 .device = 6,
92 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
93 },
94 {
95 .id = 0x04730093,
96 .device = 7,
97 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
98 ZYNQMP_VARIANT_EV,
99 },
100 {
101 .id = 0x04738093,
102 .device = 9,
103 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
104 },
105 {
106 .id = 0x04740093,
107 .device = 11,
108 .variants = ZYNQMP_VARIANT_EG,
109 },
110 {
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530111 .id = 0x04741093,
112 .device = 11,
113 .variants = ZYNQMP_VARIANT_EG_SE,
114 },
115 {
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200116 .id = 0x04750093,
117 .device = 15,
118 .variants = ZYNQMP_VARIANT_EG,
119 },
120 {
121 .id = 0x04759093,
122 .device = 17,
123 .variants = ZYNQMP_VARIANT_EG,
124 },
125 {
126 .id = 0x04758093,
127 .device = 19,
128 .variants = ZYNQMP_VARIANT_EG,
129 },
130 {
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530131 .id = 0x0475C093,
132 .device = 19,
133 .variants = ZYNQMP_VARIANT_EG_SE,
134 },
135 {
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200136 .id = 0x047E1093,
137 .device = 21,
138 .variants = ZYNQMP_VARIANT_DR,
139 },
140 {
141 .id = 0x047E3093,
142 .device = 23,
143 .variants = ZYNQMP_VARIANT_DR,
144 },
145 {
146 .id = 0x047E5093,
147 .device = 25,
148 .variants = ZYNQMP_VARIANT_DR,
149 },
150 {
151 .id = 0x047E4093,
152 .device = 27,
153 .variants = ZYNQMP_VARIANT_DR,
154 },
155 {
156 .id = 0x047E0093,
157 .device = 28,
158 .variants = ZYNQMP_VARIANT_DR,
159 },
160 {
161 .id = 0x047E2093,
162 .device = 29,
163 .variants = ZYNQMP_VARIANT_DR,
164 },
165 {
166 .id = 0x047E6093,
167 .device = 39,
168 .variants = ZYNQMP_VARIANT_DR,
169 },
170 {
171 .id = 0x047FD093,
172 .device = 43,
173 .variants = ZYNQMP_VARIANT_DR,
174 },
175 {
176 .id = 0x047F8093,
177 .device = 46,
178 .variants = ZYNQMP_VARIANT_DR,
179 },
180 {
181 .id = 0x047FF093,
182 .device = 47,
183 .variants = ZYNQMP_VARIANT_DR,
184 },
185 {
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530186 .id = 0x047FA093,
187 .device = 47,
188 .variants = ZYNQMP_VARIANT_DR_SE,
189 },
190 {
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200191 .id = 0x047FB093,
192 .device = 48,
193 .variants = ZYNQMP_VARIANT_DR,
194 },
195 {
196 .id = 0x047FE093,
197 .device = 49,
198 .variants = ZYNQMP_VARIANT_DR,
199 },
200 {
201 .id = 0x046d0093,
202 .device = 67,
203 .variants = ZYNQMP_VARIANT_DR,
204 },
205 {
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530206 .id = 0x046d7093,
207 .device = 67,
208 .variants = ZYNQMP_VARIANT_DR_SE,
209 },
210 {
Michal Simek67a5efa2023-01-18 09:25:26 +0100211 .id = 0x04712093,
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200212 .device = 24,
213 .variants = 0,
214 },
215 {
216 .id = 0x04724093,
217 .device = 26,
218 .variants = 0,
219 },
220};
221
222static const struct zynqmp_device *zynqmp_get_device(u32 idcode)
223{
224 idcode &= IDCODE_DEV_TYPE_MASK;
225
226 for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
227 if (zynqmp_devices[i].id == idcode)
228 return &zynqmp_devices[i];
229 }
230
231 return NULL;
232}
233
234static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
235 u32 idcode2)
236{
237 struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
238 const struct zynqmp_device *device;
239 int ret;
240
241 device = zynqmp_get_device(idcode);
242 if (!device)
243 return 0;
244
245 /* Add device prefix to the name */
246 ret = snprintf(priv->machine, sizeof(priv->machine), "%s%d",
247 device->variants ? "zu" : "xck", device->device);
248 if (ret < 0)
249 return ret;
250
251 if (device->variants & ZYNQMP_VARIANT_EV) {
252 /* Devices with EV variant might be EG/CG/EV family */
253 if (idcode2 & IDCODE2_PL_INIT_MASK) {
254 u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
255 EFUSE_VCU_DIS_SHIFT) << 1 |
256 ((idcode2 & EFUSE_GPU_DIS_MASK) >>
257 EFUSE_GPU_DIS_SHIFT);
258
259 /*
260 * Get family name based on extended idcode values as
261 * determined on UG1087, EXTENDED_IDCODE register
262 * description
263 */
264 switch (family) {
265 case 0x00:
266 strlcat(priv->machine, "ev",
267 sizeof(priv->machine));
268 break;
269 case 0x10:
270 strlcat(priv->machine, "eg",
271 sizeof(priv->machine));
272 break;
273 case 0x11:
274 strlcat(priv->machine, "cg",
275 sizeof(priv->machine));
276 break;
277 default:
278 /* Do not append family name*/
279 break;
280 }
281 } else {
282 /*
283 * When PL powered down the VCU Disable efuse cannot be
284 * read. So, ignore the bit and just findout if it is CG
285 * or EG/EV variant.
286 */
287 strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
288 "cg" : "e", sizeof(priv->machine));
289 }
290 } else if (device->variants & ZYNQMP_VARIANT_CG) {
291 /* Devices with CG variant might be EG or CG family */
292 strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
293 "cg" : "eg", sizeof(priv->machine));
294 } else if (device->variants & ZYNQMP_VARIANT_EG) {
295 strlcat(priv->machine, "eg", sizeof(priv->machine));
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530296 } else if (device->variants & ZYNQMP_VARIANT_EG_SE) {
297 strlcat(priv->machine, "eg_SE", sizeof(priv->machine));
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200298 } else if (device->variants & ZYNQMP_VARIANT_DR) {
299 strlcat(priv->machine, "dr", sizeof(priv->machine));
Venkatesh Yadav Abbarapu55136382024-01-23 10:27:15 +0530300 } else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
301 strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200302 }
303
304 return 0;
305}
306
T Karthik Reddy501c2062021-08-10 06:50:18 -0600307static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size)
308{
309 struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
310
311 return snprintf(buf, size, "%s", priv->family);
312}
313
Venkatesh Yadav Abbarapuf35f9572022-10-04 11:22:01 +0530314static int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size)
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200315{
316 struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
317 const char *machine = priv->machine;
318
319 if (!machine[0])
320 machine = "unknown";
321
322 return snprintf(buf, size, "%s", machine);
323}
324
T Karthik Reddy501c2062021-08-10 06:50:18 -0600325static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size)
326{
327 struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
328
329 return snprintf(buf, size, "v%d", priv->revision);
330}
331
332static const struct soc_ops soc_xilinx_zynqmp_ops = {
333 .get_family = soc_xilinx_zynqmp_get_family,
334 .get_revision = soc_xilinx_zynqmp_get_revision,
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200335 .get_machine = soc_xilinx_zynqmp_get_machine,
T Karthik Reddy501c2062021-08-10 06:50:18 -0600336};
337
338static int soc_xilinx_zynqmp_probe(struct udevice *dev)
339{
340 struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
Michal Simekab51e372022-04-20 09:39:04 +0200341 u32 ret_payload[PAYLOAD_ARG_CNT];
T Karthik Reddy501c2062021-08-10 06:50:18 -0600342 int ret;
343
344 priv->family = zynqmp_family;
345
Stefan Herbrechtsmeier4f2aeb42022-06-20 18:36:42 +0200346 if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
T Karthik Reddy501c2062021-08-10 06:50:18 -0600347 ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]);
348 else
349 ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
350 ret_payload);
351 if (ret < 0)
352 return ret;
353
354 priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK;
355
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200356 if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
357 /*
358 * Firmware returns:
359 * payload[0][31:0] = status of the operation
360 * payload[1] = IDCODE
361 * payload[2][19:0] = Version
362 * payload[2][28:20] = EXTENDED_IDCODE
363 * payload[2][29] = PL_INIT
364 */
365 u32 idcode = ret_payload[1];
366 u32 idcode2 = ret_payload[2] >>
367 ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
368 dev_dbg(dev, "IDCODE: 0x%0x, IDCODE2: 0x%0x\n", idcode,
369 idcode2);
370
371 ret = soc_xilinx_zynqmp_detect_machine(dev, idcode, idcode2);
372 if (ret)
373 return ret;
374 }
375
T Karthik Reddy501c2062021-08-10 06:50:18 -0600376 return 0;
377}
378
379U_BOOT_DRIVER(soc_xilinx_zynqmp) = {
380 .name = "soc_xilinx_zynqmp",
381 .id = UCLASS_SOC,
382 .ops = &soc_xilinx_zynqmp_ops,
383 .probe = soc_xilinx_zynqmp_probe,
384 .priv_auto = sizeof(struct soc_xilinx_zynqmp_priv),
385 .flags = DM_FLAG_PRE_RELOC,
386};