blob: ecdf6a031ec31b197bc8fb799cbf1275020703cb [file] [log] [blame]
Michal Simeke60148d2014-01-14 14:21:52 +01001/*
2 * Copyright (c) 2014 Xilinx, Inc. Michal Simek
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
12 LENGTH = CONFIG_SPL_MAX_SIZE }
13MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
14 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
15
16OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
17OUTPUT_ARCH(arm)
18ENTRY(_start)
19SECTIONS
20{
21 . = ALIGN(4);
22 .text :
23 {
24 __image_copy_start = .;
Peter Crosthwaite8a0e77b2014-08-07 22:26:43 +100025 *(.vectors)
Michal Simeke60148d2014-01-14 14:21:52 +010026 CPUDIR/start.o (.text*)
27 *(.text*)
28 } > .sram
29
30 . = ALIGN(4);
31 .rodata : {
32 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
33 } > .sram
34
35 . = ALIGN(4);
36 .data : {
37 *(.data*)
38 } > .sram
39
40 . = ALIGN(4);
Simon Glass60933362015-10-17 19:41:23 -060041#ifdef CONFIG_SPL_DM
42 .u_boot_list : {
43 KEEP(*(SORT(.u_boot_list_*_driver_*)));
44 KEEP(*(SORT(.u_boot_list_*_uclass_*)));
45 } > .sram
46
47 . = ALIGN(4);
48#endif
Michal Simeke60148d2014-01-14 14:21:52 +010049
50 . = .;
51
Simon Glass60933362015-10-17 19:41:23 -060052 _image_binary_end = .;
Michal Simeke60148d2014-01-14 14:21:52 +010053
54 _end = .;
55
56 /* Move BSS section to RAM because of FAT */
57 .bss (NOLOAD) : {
58 __bss_start = .;
59 *(.bss*)
60 . = ALIGN(4);
61 __bss_end = .;
62 } > .sdram
63
64 /DISCARD/ : { *(.dynsym) }
65 /DISCARD/ : { *(.dynstr*) }
66 /DISCARD/ : { *(.dynamic*) }
67 /DISCARD/ : { *(.plt*) }
68 /DISCARD/ : { *(.interp*) }
69 /DISCARD/ : { *(.gnu*) }
70}