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git01.mediatek.com / filogic / uboot / 54d93e2e523074a7c6f236d52328e2c5b2250ff2 / . / arch / arm / dts / tegra20-ventana.dts
blob: 939e567d1334f8de272f8a35d4cec7ba142783a6 [file] [log] [blame]
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Ventana evaluation board";
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uartd;
11 };
12
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]15 sdhci0 = "/sdhci@c8000600";
16 sdhci1 = "/sdhci@c8000400";
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]17 };
18
19 memory {
20 reg = <0x00000000 0x40000000>;
21 };
22
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]23 host1x {
24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]34 serial@70006300 {
35 clock-frequency = < 216000000 >;
36 };
37
38 i2c@7000c000 {
39 status = "disabled";
40 };
41
42 i2c@7000c400 {
43 status = "disabled";
44 };
45
46 i2c@7000c500 {
47 status = "disabled";
48 };
49
50 i2c@7000d000 {
51 status = "disabled";
52 };
53
54 usb@c5000000 {
55 status = "disabled";
56 };
57
58 usb@c5004000 {
59 status = "disabled";
60 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]61
62 sdhci@c8000400 {
63 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]64 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
65 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
66 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]67 bus-width = <4>;
68 };
69
70 sdhci@c8000600 {
71 status = "okay";
72 bus-width = <8>;
73 };
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]74
75 lcd_panel: panel {
76 clock = <72072000>;
77 xres = <1366>;
78 yres = <768>;
79 left-margin = <58>;
80 right-margin = <58>;
81 hsync-len = <58>;
82 lower-margin = <4>;
83 upper-margin = <4>;
84 vsync-len = <4>;
85 hsync-active-high;
86 vsync-active-high;
87 nvidia,bits-per-pixel = <16>;
88 nvidia,pwm = <&pwm 2 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]89 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
90 GPIO_ACTIVE_HIGH>;
91 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
92 GPIO_ACTIVE_HIGH>;
93 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
94 GPIO_ACTIVE_HIGH>;
95 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
96 GPIO_ACTIVE_HIGH>;
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]97 nvidia,panel-timings = <0 0 200 0 0>;
98 };
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]99};