blob: 68df0a79c4e5e3a5ada00ae686bb1403f0a2453c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek72536fd2015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
Michal Simek72536fd2015-11-20 13:17:22 +01006 */
7
8#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Michal Simek72536fd2015-11-20 13:17:22 +010010#include <spl.h>
11
12#include <asm/io.h>
13#include <asm/spl.h>
14#include <asm/arch/hardware.h>
Michal Simekef955012019-12-03 15:02:50 +010015#include <asm/arch/psu_init_gpl.h>
Michal Simek72536fd2015-11-20 13:17:22 +010016#include <asm/arch/sys_proto.h>
17
18void board_init_f(ulong dummy)
19{
Michal Simeke0f36102017-07-12 13:08:41 +020020 board_early_init_f();
Michal Simek72536fd2015-11-20 13:17:22 +010021 board_early_init_r();
Michal Simek72536fd2015-11-20 13:17:22 +010022}
23
Michal Simek3eb32de2016-08-15 09:41:36 +020024static void ps_mode_reset(ulong mode)
25{
Michal Simek3eb32de2016-08-15 09:41:36 +020026 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
27 &crlapb_base->boot_pin_ctrl);
28 udelay(5);
29 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
30 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
31 &crlapb_base->boot_pin_ctrl);
32}
33
34/*
35 * Set default PS_MODE1 which is used for USB ULPI phy reset
36 * Also other resets can be connected to this certain pin
37 */
38#ifndef MODE_RESET
39# define MODE_RESET PS_MODE1
40#endif
41
Michal Simek72536fd2015-11-20 13:17:22 +010042#ifdef CONFIG_SPL_BOARD_INIT
43void spl_board_init(void)
44{
45 preloader_console_init();
Michal Simek3eb32de2016-08-15 09:41:36 +020046 ps_mode_reset(MODE_RESET);
Michal Simek72536fd2015-11-20 13:17:22 +010047 board_init();
Michal Simekef955012019-12-03 15:02:50 +010048 psu_post_config_data();
Michal Simek72536fd2015-11-20 13:17:22 +010049}
50#endif
51
Michal Simek6d651d92019-12-09 13:00:57 +010052void board_boot_order(u32 *spl_boot_list)
53{
54 spl_boot_list[0] = spl_boot_device();
55
56 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
57 spl_boot_list[1] = BOOT_DEVICE_MMC2;
58 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
59 spl_boot_list[1] = BOOT_DEVICE_MMC1;
Michal Simek2642eb72020-03-11 15:00:51 +010060
61 spl_boot_list[2] = BOOT_DEVICE_RAM;
Michal Simek6d651d92019-12-09 13:00:57 +010062}
63
Michal Simek72536fd2015-11-20 13:17:22 +010064u32 spl_boot_device(void)
65{
66 u32 reg = 0;
67 u8 bootmode;
68
Michal Simek94ddcaa2016-08-30 16:17:27 +020069#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
70 /* Change default boot mode at run-time */
Michal Simek833e0c42016-10-25 11:43:02 +020071 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek94ddcaa2016-08-30 16:17:27 +020072 &crlapb_base->boot_mode);
73#endif
74
Michal Simek72536fd2015-11-20 13:17:22 +010075 reg = readl(&crlapb_base->boot_mode);
Michal Simek833e0c42016-10-25 11:43:02 +020076 if (reg >> BOOT_MODE_ALT_SHIFT)
77 reg >>= BOOT_MODE_ALT_SHIFT;
78
Michal Simek72536fd2015-11-20 13:17:22 +010079 bootmode = reg & BOOT_MODES_MASK;
80
81 switch (bootmode) {
82 case JTAG_MODE:
83 return BOOT_DEVICE_RAM;
84#ifdef CONFIG_SPL_MMC_SUPPORT
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040085 case SD_MODE1:
Michal Simeka8896202017-03-02 11:02:55 +010086 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040087 return BOOT_DEVICE_MMC2;
Michal Simek72536fd2015-11-20 13:17:22 +010088 case SD_MODE:
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -040089 case EMMC_MODE:
Michal Simek72536fd2015-11-20 13:17:22 +010090 return BOOT_DEVICE_MMC1;
91#endif
Andrew F. Davis6d932e62019-01-17 13:43:02 -060092#ifdef CONFIG_SPL_DFU
Michal Simek12398ea2016-08-19 14:14:52 +020093 case USB_MODE:
94 return BOOT_DEVICE_DFU;
95#endif
Michal Simek2740d372016-10-26 09:24:32 +020096#ifdef CONFIG_SPL_SATA_SUPPORT
97 case SW_SATA_MODE:
98 return BOOT_DEVICE_SATA;
99#endif
Michal Simek1b19a6f2017-11-02 09:15:05 +0100100#ifdef CONFIG_SPL_SPI_SUPPORT
101 case QSPI_MODE_24BIT:
102 case QSPI_MODE_32BIT:
103 return BOOT_DEVICE_SPI;
104#endif
Michal Simek72536fd2015-11-20 13:17:22 +0100105 default:
106 printf("Invalid Boot Mode:0x%x\n", bootmode);
107 break;
108 }
109
110 return 0;
111}
112
Michal Simek72536fd2015-11-20 13:17:22 +0100113#ifdef CONFIG_SPL_OS_BOOT
114int spl_start_uboot(void)
115{
Michal Simek72536fd2015-11-20 13:17:22 +0100116 return 0;
117}
118#endif
119
120#ifdef CONFIG_SPL_LOAD_FIT
121int board_fit_config_name_match(const char *name)
122{
123 /* Just empty function now - can't decide what to choose */
124 debug("%s: %s\n", __func__, name);
125
Michal Simek6b7515f2019-12-09 08:39:19 +0100126 return -1;
Michal Simek72536fd2015-11-20 13:17:22 +0100127}
128#endif