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git01.mediatek.com / filogic / uboot / 54983813ff6def15076c6dd209b38b8a6dea61d2 / . / arch / m68k / cpu / mcf547x_8x / start.S
blob: 2296f9a52311dc3555dcb54762aa0059de90c43a [file] [log] [blame]
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]6 */
7
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]8#include <asm-offsets.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]9#include <config.h>
10#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]11#include <asm/cache.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]12
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]13#define _START _start
14#define _FAULT _fault
15
16#define SAVE_ALL \
17 move.w #0x2700,%sr; /* disable intrs */ \
18 subl #60,%sp; /* space for 15 regs */ \
19 moveml %d0-%d7/%a0-%a6,%sp@;
20
21#define RESTORE_ALL \
22 moveml %sp@,%d0-%d7/%a0-%a6; \
23 addl #60,%sp; /* space for 15 regs */ \
24 rte;
25
26.text
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]27
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]28/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]29 * Vector table. This is used for initial platform startup.
30 * These vectors are to catch any un-intended traps.
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]31 */
32_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]33INITSP: .long 0x00000000 /* Initial SP */
34INITPC: .long _START /* Initial PC */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]35
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]36vector02_0F:
37.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
38.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]39
40/* Reserved */
41vector10_17:
42.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
43
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]44vector18_1F:
45.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]46
47/* TRAP #0 - #15 */
48vector20_2F:
49.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
50.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
51
52/* Reserved */
53vector30_3F:
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
56
57vector64_127:
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66
67vector128_191:
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77vector192_255:
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]87.text
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]88
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]89.globl _start
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]90_start:
91 nop
92 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]93 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]94
95 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]96 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]97 movec %d0, %VBR
98
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]99 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]100 movec %d0, %RAMBAR0
101
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]102 move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]103 movec %d0, %RAMBAR1
104
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]105 move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]106 move.c %d0, %MBAR
107
108 /* invalidate and disable cache */
109 move.l #0x01040100, %d0 /* Invalidate cache cmd */
110 movec %d0, %CACR /* Invalidate cache */
111 move.l #0, %d0
112 movec %d0, %ACR0
113 movec %d0, %ACR1
114 movec %d0, %ACR2
115 movec %d0, %ACR3
116
117 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]118 move.l #0, %d0
119 move.l #(ICACHE_STATUS), %a1 /* icache */
120 move.l #(DCACHE_STATUS), %a2 /* icache */
121 move.l %d0, (%a1)
122 move.l %d0, (%a2)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]123
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]124 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]125 move.l #__got_start, %a5
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]126
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]127 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]128 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]129
130 /*
131 * if configured, malloc_f arena will be reserved first,
132 * then (and always) gd struct space will be reserved
133 */
134 move.l %sp, -(%sp)
135 bsr board_init_f_alloc_reserve
136
137 /* update stack and frame-pointers */
138 move.l %d0, %sp
139 move.l %sp, %fp
140
141 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]142 move.l %d0, -(%sp)
143 bsr board_init_f_init_reserve
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]144
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]145 /* run low-level CPU init code (from flash) */
146 jbsr cpu_init_f
147
148 /* run low-level board init code (from flash) */
149 clr.l %sp@-
150 jbsr board_init_f
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]151
152 /* board_init_f() does not return */
153
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]154/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]155
156/*
157 * void relocate_code (addr_sp, gd, addr_moni)
158 *
159 * This "function" does not return, instead it continues in RAM
160 * after relocating the monitor code.
161 *
162 * r3 = dest
163 * r4 = src
164 * r5 = length in bytes
165 * r6 = cachelinesize
166 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]167.globl relocate_code
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]168relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]169 link.w %a6,#0
170 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]171
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]172 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
173 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]174
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]175 move.l #CONFIG_SYS_MONITOR_BASE, %a1
176 move.l #__init_end, %a2
177 move.l %a0, %a3
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]178
179 /* copy the code to RAM */
1801:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]181 move.l (%a1)+, (%a3)+
182 cmp.l %a1,%a2
183 bgt.s 1b
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]184
185/*
186 * We are done. Do not return, instead branch to second part of board
187 * initialization, now running from RAM.
188 */
189 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]190 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]191 jmp (%a1)
192
193in_ram:
194
195clear_bss:
196 /*
197 * Now clear BSS segment
198 */
199 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]200 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]201 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]202 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]2036:
204 clr.l (%a1)+
205 cmp.l %a1,%d1
206 bgt.s 6b
207
208 /*
209 * fix got table in RAM
210 */
211 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]212 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]213 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]214
215 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]216 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]217
2187:
219 move.l (%a1),%d1
220 sub.l #_start,%d1
221 add.l %a0,%d1
222 move.l %d1,(%a1)+
223 cmp.l %a2, %a1
224 bne 7b
225
226 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]227 move.l %a0, %a1
228 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]229
230 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]231 move.l %a0,-(%sp) /* dest_addr */
232 move.l %d0,-(%sp) /* gd */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]233 jsr (%a1)
234
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]235/******************************************************************************/
236
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]237/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]238.globl _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]239_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]240 bra _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]241
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]242.globl _exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]243_exc_handler:
244 SAVE_ALL
245 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]246 bsr exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]247 addql #4,%sp
248 RESTORE_ALL
249
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]250.globl _int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]251_int_handler:
252 SAVE_ALL
253 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]254 bsr int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]255 addql #4,%sp
256 RESTORE_ALL
257
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]258/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]259
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]260.globl version_string
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]261version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]262.ascii U_BOOT_VERSION_STRING, "\0"
263.align 4