blob: 32a2836f0bf15a58ea4286c01dabceb0dbc01378 [file] [log] [blame]
Simon Glass5e5c0cd2019-12-06 21:41:53 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#define LOG_CATEGORY UCLASS_ACPI_PMC
7
8#include <common.h>
Simon Glass5e5c0cd2019-12-06 21:41:53 -07009#include <dm.h>
10#include <log.h>
Simon Glass50461092020-04-08 16:57:35 -060011#include <acpi/acpi_s3.h>
Simon Glasse63ca972019-12-06 21:42:57 -070012#ifdef CONFIG_X86
13#include <asm/intel_pinctrl.h>
14#endif
Simon Glass5e5c0cd2019-12-06 21:41:53 -070015#include <asm/io.h>
16#include <power/acpi_pmc.h>
17
Simon Glass5e5c0cd2019-12-06 21:41:53 -070018struct tco_regs {
19 u32 tco_rld;
20 u32 tco_sts;
21 u32 tco1_cnt;
22 u32 tco_tmr;
23};
24
25enum {
26 TCO_STS_TIMEOUT = 1 << 3,
27 TCO_STS_SECOND_TO_STS = 1 << 17,
28 TCO1_CNT_HLT = 1 << 11,
29};
30
Simon Glasse63ca972019-12-06 21:42:57 -070031#ifdef CONFIG_X86
32static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum)
33{
34 return upriv->gpe0_dwx_shift_base + regnum * 4;
35}
36
37int pmc_gpe_init(struct udevice *dev)
38{
39 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
40 struct udevice *itss;
41 u32 *dw;
42 u32 gpio_cfg_mask;
43 u32 gpio_cfg;
44 int ret, i;
45 u32 mask;
46
47 if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC)
48 return log_msg_ret("uclass", -EPROTONOSUPPORT);
49 dw = upriv->gpe0_dw;
50 mask = upriv->gpe0_dwx_mask;
51 gpio_cfg_mask = 0;
52 for (i = 0; i < upriv->gpe0_count; i++) {
53 gpio_cfg_mask |= mask << gpe0_shift(upriv, i);
54 if (dw[i] & ~mask)
55 return log_msg_ret("Base GPE0 value", -EINVAL);
56 }
57
58 /*
59 * Route the GPIOs to the GPE0 block. Determine that all values
60 * are different and if they aren't, use the reset values.
61 */
62 if (dw[0] == dw[1] || dw[1] == dw[2]) {
63 log_info("PMC: Using default GPE route");
64 gpio_cfg = readl(upriv->gpe_cfg);
65 for (i = 0; i < upriv->gpe0_count; i++)
66 dw[i] = gpio_cfg >> gpe0_shift(upriv, i);
67 } else {
68 gpio_cfg = 0;
69 for (i = 0; i < upriv->gpe0_count; i++)
70 gpio_cfg |= dw[i] << gpe0_shift(upriv, i);
71 clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg);
72 }
73
74 /* Set the routes in the GPIO communities as well */
75 ret = uclass_first_device_err(UCLASS_IRQ, &itss);
76 if (ret)
77 return log_msg_ret("Cannot find itss", ret);
78 pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]);
79
80 return 0;
81}
82#endif /* CONFIG_X86 */
83
Simon Glass5e5c0cd2019-12-06 21:41:53 -070084static void pmc_fill_pm_reg_info(struct udevice *dev)
85{
86 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
87 int i;
88
89 upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
90 upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
91 upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
92
93 log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
94 upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
95
96 for (i = 0; i < GPE0_REG_MAX; i++) {
97 upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
98 upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
99 log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
100 upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
101 }
102}
103
104int pmc_disable_tco_base(ulong tco_base)
105{
106 struct tco_regs *regs = (struct tco_regs *)tco_base;
107
108 debug("tco_base %lx = %x\n", (ulong)&regs->tco1_cnt, TCO1_CNT_HLT);
109 setio_32(&regs->tco1_cnt, TCO1_CNT_HLT);
110
111 return 0;
112}
113
114int pmc_init(struct udevice *dev)
115{
116 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
117 int ret;
118
119 pmc_fill_pm_reg_info(dev);
120 if (!ops->init)
121 return -ENOSYS;
122
123 ret = ops->init(dev);
124 if (ret)
125 return log_msg_ret("Failed to init pmc", ret);
126
127#ifdef DEBUG
128 pmc_dump_info(dev);
129#endif
130
131 return 0;
132}
133
134int pmc_prev_sleep_state(struct udevice *dev)
135{
136 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
137 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
138 int prev_sleep_state = ACPI_S0; /* Default to S0 */
139
140 if (upriv->pm1_sts & WAK_STS) {
141 switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) {
142 case ACPI_S3:
143 if (IS_ENABLED(HAVE_ACPI_RESUME))
144 prev_sleep_state = ACPI_S3;
145 break;
146 case ACPI_S5:
147 prev_sleep_state = ACPI_S5;
148 break;
149 default:
150 break;
151 }
152
153 /* Clear SLP_TYP */
154 outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT);
155 }
156
157 if (!ops->prev_sleep_state)
158 return prev_sleep_state;
159
160 return ops->prev_sleep_state(dev, prev_sleep_state);
161}
162
163int pmc_disable_tco(struct udevice *dev)
164{
165 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
166
167 pmc_fill_pm_reg_info(dev);
168 if (!ops->disable_tco)
169 return -ENOSYS;
170
171 return ops->disable_tco(dev);
172}
173
174int pmc_global_reset_set_enable(struct udevice *dev, bool enable)
175{
176 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
177
178 if (!ops->global_reset_set_enable)
179 return -ENOSYS;
180
181 return ops->global_reset_set_enable(dev, enable);
182}
183
184void pmc_dump_info(struct udevice *dev)
185{
186 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
187 int i;
188
189 printf("Device: %s\n", dev->name);
190 printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n",
191 upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2,
192 upriv->gpe_cfg);
193 printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
194 upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
195
196 for (i = 0; i < GPE0_REG_MAX; i++) {
197 printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
198 upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
199 }
200
201 printf("prsts: %08x\n", upriv->prsts);
202 printf("tco_sts: %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts);
203 printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
204 upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
205}
206
Simon Glassb75b15b2020-12-03 16:55:23 -0700207int pmc_ofdata_to_uc_plat(struct udevice *dev)
Simon Glass5e5c0cd2019-12-06 21:41:53 -0700208{
209 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
210 int ret;
211
212 ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask);
213 if (ret)
214 return log_msg_ret("no gpe0-dwx-mask", ret);
215 ret = dev_read_u32(dev, "gpe0-dwx-shift-base",
216 &upriv->gpe0_dwx_shift_base);
217 if (ret)
218 return log_msg_ret("no gpe0-dwx-shift-base", ret);
219 ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg);
220 if (ret)
221 return log_msg_ret("no gpe0-sts", ret);
222 upriv->gpe0_sts_reg += upriv->acpi_base;
223 ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg);
224 if (ret)
225 return log_msg_ret("no gpe0-en", ret);
226 upriv->gpe0_en_reg += upriv->acpi_base;
227
228 return 0;
229}
230
231UCLASS_DRIVER(acpi_pmc) = {
232 .id = UCLASS_ACPI_PMC,
233 .name = "power-mgr",
Simon Glass8a2b47f2020-12-03 16:55:17 -0700234 .per_device_auto = sizeof(struct acpi_pmc_upriv),
Simon Glass5e5c0cd2019-12-06 21:41:53 -0700235};