blob: 41540d8ebc63e07206eb73e2b87c6236ae99a296 [file] [log] [blame]
Simon Glass83490512019-12-06 21:42:54 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <fdtdec.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass83490512019-12-06 21:42:54 -070011#include <p2sb.h>
12#include <pch.h>
13#include <pci.h>
14#include <syscon.h>
Simon Glassaac86da2020-07-07 21:32:26 -060015#include <acpi/acpi_device.h>
Simon Glass83490512019-12-06 21:42:54 -070016#include <asm/cpu.h>
17#include <asm/gpio.h>
18#include <asm/intel_pinctrl.h>
19#include <asm/intel_pinctrl_defs.h>
20#include <asm/io.h>
21#include <asm/pci.h>
22#include <asm/arch/gpio.h>
Simon Glassaac86da2020-07-07 21:32:26 -060023#include <dm/acpi.h>
Simon Glass83490512019-12-06 21:42:54 -070024#include <dt-bindings/gpio/x86-gpio.h>
25
26static int intel_gpio_direction_input(struct udevice *dev, uint offset)
27{
28 struct udevice *pinctrl = dev_get_parent(dev);
Simon Glass25f16c12020-07-07 21:32:19 -060029 uint config_offset;
30
31 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
Simon Glass83490512019-12-06 21:42:54 -070032
33 pcr_clrsetbits32(pinctrl, config_offset,
34 PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
35 PAD_CFG0_RX_DISABLE,
36 PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
37
38 return 0;
39}
40
41static int intel_gpio_direction_output(struct udevice *dev, uint offset,
42 int value)
43{
44 struct udevice *pinctrl = dev_get_parent(dev);
Simon Glass25f16c12020-07-07 21:32:19 -060045 uint config_offset;
46
47 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
Simon Glass83490512019-12-06 21:42:54 -070048
Wolfgang Wallnerc3d53e12020-02-03 11:38:04 +010049 pcr_clrsetbits32(pinctrl, config_offset,
Simon Glass83490512019-12-06 21:42:54 -070050 PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
Wolfgang Wallneree2ba392020-02-03 11:38:05 +010051 PAD_CFG0_TX_DISABLE | PAD_CFG0_TX_STATE,
Simon Glass83490512019-12-06 21:42:54 -070052 PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
53 (value ? PAD_CFG0_TX_STATE : 0));
54
55 return 0;
56}
57
58static int intel_gpio_get_value(struct udevice *dev, uint offset)
59{
60 struct udevice *pinctrl = dev_get_parent(dev);
61 uint mode, rx_tx;
62 u32 reg;
63
64 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
65 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
66 if (!mode) {
67 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
68 if (rx_tx == PAD_CFG0_TX_DISABLE)
Wolfgang Wallner1ec382a2020-02-03 11:38:06 +010069 return reg & PAD_CFG0_RX_STATE ? 1 : 0;
Simon Glass83490512019-12-06 21:42:54 -070070 else if (rx_tx == PAD_CFG0_RX_DISABLE)
Wolfgang Wallner1ec382a2020-02-03 11:38:06 +010071 return reg & PAD_CFG0_TX_STATE ? 1 : 0;
Simon Glass83490512019-12-06 21:42:54 -070072 }
73
74 return 0;
75}
76
Simon Glass25f16c12020-07-07 21:32:19 -060077static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
78 int value)
Simon Glass83490512019-12-06 21:42:54 -070079{
80 struct udevice *pinctrl = dev_get_parent(dev);
Simon Glass25f16c12020-07-07 21:32:19 -060081 uint config_offset;
82
83 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
Simon Glass83490512019-12-06 21:42:54 -070084
Wolfgang Wallnerc3d53e12020-02-03 11:38:04 +010085 pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
Simon Glass83490512019-12-06 21:42:54 -070086 value ? PAD_CFG0_TX_STATE : 0);
87
88 return 0;
89}
90
91static int intel_gpio_get_function(struct udevice *dev, uint offset)
92{
93 struct udevice *pinctrl = dev_get_parent(dev);
94 uint mode, rx_tx;
95 u32 reg;
96
97 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
98 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
99 if (!mode) {
100 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
101 if (rx_tx == PAD_CFG0_TX_DISABLE)
102 return GPIOF_INPUT;
103 else if (rx_tx == PAD_CFG0_RX_DISABLE)
104 return GPIOF_OUTPUT;
105 }
106
107 return GPIOF_FUNC;
108}
109
110static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
111 struct ofnode_phandle_args *args)
112{
113 struct udevice *pinctrl, *dev;
114 int gpio, ret;
115
116 /*
117 * GPIO numbers are global in the device tree so it doesn't matter
118 * which one is used
119 */
120 gpio = args->args[0];
121 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
122 if (ret)
123 return log_msg_ret("bad", ret);
124 device_find_first_child(pinctrl, &dev);
125 if (!dev)
126 return log_msg_ret("no child", -ENOENT);
127 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
128 desc->dev = dev;
129
130 return 0;
131}
132
Simon Glassaac86da2020-07-07 21:32:26 -0600133#if CONFIG_IS_ENABLED(ACPIGEN)
134static int intel_gpio_get_acpi(const struct gpio_desc *desc,
135 struct acpi_gpio *gpio)
136{
137 struct udevice *pinctrl;
138 int ret;
139
140 if (!dm_gpio_is_valid(desc))
141 return -ENOENT;
142 pinctrl = dev_get_parent(desc->dev);
143
144 memset(gpio, '\0', sizeof(*gpio));
145
146 gpio->type = ACPI_GPIO_TYPE_IO;
147 gpio->pull = ACPI_GPIO_PULL_DEFAULT;
148 gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
149 gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
150 gpio->pin_count = 1;
151 gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
152 gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
153 desc->offset);
154 ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
155 if (ret)
156 return log_msg_ret("resource", ret);
157
158 return 0;
159}
160#endif
161
Simon Glass83490512019-12-06 21:42:54 -0700162static int intel_gpio_probe(struct udevice *dev)
163{
164 return 0;
165}
166
Simon Glassaad29ae2020-12-03 16:55:21 -0700167static int intel_gpio_of_to_plat(struct udevice *dev)
Simon Glass83490512019-12-06 21:42:54 -0700168{
169 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
170 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
171 const struct pad_community *comm = pinctrl_priv->comm;
172
173 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
174 upriv->bank_name = dev->name;
175
176 return 0;
177}
178
179static const struct dm_gpio_ops gpio_intel_ops = {
180 .direction_input = intel_gpio_direction_input,
181 .direction_output = intel_gpio_direction_output,
182 .get_value = intel_gpio_get_value,
183 .set_value = intel_gpio_set_value,
184 .get_function = intel_gpio_get_function,
185 .xlate = intel_gpio_xlate,
Simon Glassaac86da2020-07-07 21:32:26 -0600186#if CONFIG_IS_ENABLED(ACPIGEN)
187 .get_acpi = intel_gpio_get_acpi,
188#endif
Simon Glass83490512019-12-06 21:42:54 -0700189};
190
191static const struct udevice_id intel_intel_gpio_ids[] = {
192 { .compatible = "intel,gpio" },
193 { }
194};
195
Simon Glassa055da82020-10-05 05:27:01 -0600196U_BOOT_DRIVER(intel_gpio) = {
197 .name = "intel_gpio",
Simon Glass83490512019-12-06 21:42:54 -0700198 .id = UCLASS_GPIO,
199 .of_match = intel_intel_gpio_ids,
200 .ops = &gpio_intel_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -0700201 .of_to_plat = intel_gpio_of_to_plat,
Simon Glass83490512019-12-06 21:42:54 -0700202 .probe = intel_gpio_probe,
203};