Stefan Agner | 1f5925a | 2014-09-12 13:06:36 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
Tom Rini | ec3f662 | 2018-10-26 08:40:53 -0400 | [diff] [blame] | 2 | CONFIG_SYS_THUMB_BUILD=y |
3 | # CONFIG_SPL_SYS_THUMB_BUILD is not set | ||||
Stefan Agner | d53c0a4 | 2017-03-13 18:41:36 -0700 | [diff] [blame] | 4 | CONFIG_ARCH_VF610=y |
Tom Rini | 07edfae | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 5 | CONFIG_SYS_TEXT_BASE=0x3f401000 |
Tom Rini | f226038 | 2018-08-16 08:16:24 -0400 | [diff] [blame] | 6 | CONFIG_NR_DRAM_BANKS=1 |
Simon Glass | 73c18b4 | 2017-07-23 21:19:39 -0600 | [diff] [blame] | 7 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" |
Heiko Schocher | 0b368b1 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 8 | CONFIG_BOOTDELAY=3 |
Masahiro Yamada | bf9c293 | 2017-09-16 14:10:40 +0900 | [diff] [blame] | 9 | CONFIG_LOGLEVEL=3 |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 10 | CONFIG_BOARD_EARLY_INIT_F=y |
Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 11 | CONFIG_HUSH_PARSER=y |
Adam Ford | 58dbf86 | 2018-02-06 07:58:59 -0600 | [diff] [blame] | 12 | # CONFIG_CMDLINE_EDITING is not set |
13 | # CONFIG_AUTO_COMPLETE is not set | ||||
Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 14 | CONFIG_CMD_BOOTZ=y |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 15 | CONFIG_CMD_MEMTEST=y |
Simon Glass | 18980cc | 2017-05-17 03:25:22 -0600 | [diff] [blame] | 16 | CONFIG_CMD_FUSE=y |
Bhuvanchandra DV | 7db0d33 | 2016-01-27 10:31:50 +0530 | [diff] [blame] | 17 | CONFIG_CMD_GPIO=y |
Tom Rini | 78873cd | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 18 | CONFIG_CMD_I2C=y |
19 | CONFIG_CMD_MMC=y | ||||
20 | CONFIG_CMD_NAND_TRIMFFS=y | ||||
Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 21 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 22 | CONFIG_CMD_DHCP=y |
Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 23 | CONFIG_CMD_MII=y |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 24 | CONFIG_CMD_PING=y |
Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 25 | CONFIG_CMD_FAT=y |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 26 | CONFIG_MTDIDS_DEFAULT="nand0=fsl_nfc" |
27 | CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_nfc:128k(vf-bcb)ro,1408k(u-boot)ro,512k(u-boot-env),4m(kernel),512k(fdt),-(rootfs)" | ||||
Heiko Schocher | 09dbb85 | 2016-09-21 07:58:19 +0200 | [diff] [blame] | 28 | CONFIG_CMD_UBI=y |
Bhuvanchandra DV | 7db0d33 | 2016-01-27 10:31:50 +0530 | [diff] [blame] | 29 | CONFIG_OF_CONTROL=y |
Tom Rini | 7406032 | 2018-09-03 15:26:12 -0400 | [diff] [blame] | 30 | CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" |
Tom Rini | 5b0b040 | 2017-08-28 07:16:32 -0400 | [diff] [blame] | 31 | CONFIG_ENV_IS_IN_NAND=y |
Bhuvanchandra DV | 7db0d33 | 2016-01-27 10:31:50 +0530 | [diff] [blame] | 32 | CONFIG_DM=y |
Tom Rini | afea41d | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 33 | CONFIG_DM_GPIO=y |
Bhuvanchandra DV | 7db0d33 | 2016-01-27 10:31:50 +0530 | [diff] [blame] | 34 | CONFIG_VYBRID_GPIO=y |
Yangbo Lu | 7334038 | 2019-06-21 11:42:28 +0800 | [diff] [blame] | 35 | CONFIG_FSL_ESDHC_IMX=y |
Stefan Agner | 6120f75 | 2015-05-08 19:07:11 +0200 | [diff] [blame] | 36 | CONFIG_NAND_VF610_NFC=y |
37 | CONFIG_SYS_NAND_BUSWIDTH_16BIT=y | ||||
Alexandru Gagniuc | d83e98c | 2017-08-01 17:19:59 -0700 | [diff] [blame] | 38 | CONFIG_PHYLIB=y |
Alexandru Gagniuc | 4e24ff6 | 2017-08-01 17:20:00 -0700 | [diff] [blame] | 39 | CONFIG_PHY_MICREL=y |
James Byrne | bc292c2 | 2019-03-06 12:48:27 +0000 | [diff] [blame] | 40 | CONFIG_PHY_MICREL_KSZ8XXX=y |
Adam Ford | 5370547 | 2018-07-20 23:03:57 -0500 | [diff] [blame] | 41 | CONFIG_MII=y |
Tom Rini | afea41d | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 42 | CONFIG_DM_SERIAL=y |
Bin Meng | 4409dcf | 2016-01-13 19:39:00 -0800 | [diff] [blame] | 43 | CONFIG_FSL_LPUART=y |
Heinrich Schuchardt | 087adbe | 2018-10-16 18:47:58 +0200 | [diff] [blame] | 44 | # CONFIG_EFI_LOADER is not set |