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git01.mediatek.com / filogic / uboot / 53a7e98bb7c18da01a84bdfaa5525b9929b973a4 / . / drivers / reset / stm32 / stm32-reset-mp25.c
blob: 91c0336bc58afd3044523af73c8267a071d319d3 [file] [log] [blame]
Gabriel Fernandezafdc1ae2025-05-27 15:27:53 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
4 * Author(s): Gabriel Fernandez, <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dm.h>
8#include <stm32-reset-core.h>
9#include <stm32mp25_rcc.h>
10#include <dt-bindings/reset/st,stm32mp25-rcc.h>
11
12/* Reset clear offset for STM32MP RCC */
13#define RCC_CLR_OFFSET 0x4
14
15/* Timeout for deassert */
16#define STM32_DEASSERT_TIMEOUT_US 10000
17
18#define RESET(id, _offset, _bit_idx, _set_clr) \
19 [id] = &(struct stm32_reset_cfg){ \
20 .offset = (_offset), \
21 .bit_idx = (_bit_idx), \
22 .set_clr = (_set_clr), \
23 }
24
25static const struct stm32_reset_cfg *stm32mp25_reset[STM32MP25_LAST_RESET] = {
26 RESET(TIM1_R, RCC_TIM1CFGR, 0, 0),
27 RESET(TIM2_R, RCC_TIM2CFGR, 0, 0),
28 RESET(TIM3_R, RCC_TIM3CFGR, 0, 0),
29 RESET(TIM4_R, RCC_TIM4CFGR, 0, 0),
30 RESET(TIM5_R, RCC_TIM5CFGR, 0, 0),
31 RESET(TIM6_R, RCC_TIM6CFGR, 0, 0),
32 RESET(TIM7_R, RCC_TIM7CFGR, 0, 0),
33 RESET(TIM8_R, RCC_TIM8CFGR, 0, 0),
34 RESET(TIM10_R, RCC_TIM10CFGR, 0, 0),
35 RESET(TIM11_R, RCC_TIM11CFGR, 0, 0),
36 RESET(TIM12_R, RCC_TIM12CFGR, 0, 0),
37 RESET(TIM13_R, RCC_TIM13CFGR, 0, 0),
38 RESET(TIM14_R, RCC_TIM14CFGR, 0, 0),
39 RESET(TIM15_R, RCC_TIM15CFGR, 0, 0),
40 RESET(TIM16_R, RCC_TIM16CFGR, 0, 0),
41 RESET(TIM17_R, RCC_TIM17CFGR, 0, 0),
42 RESET(TIM20_R, RCC_TIM20CFGR, 0, 0),
43 RESET(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),
44 RESET(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),
45 RESET(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),
46 RESET(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),
47 RESET(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),
48 RESET(SPI1_R, RCC_SPI1CFGR, 0, 0),
49 RESET(SPI2_R, RCC_SPI2CFGR, 0, 0),
50 RESET(SPI3_R, RCC_SPI3CFGR, 0, 0),
51 RESET(SPI4_R, RCC_SPI4CFGR, 0, 0),
52 RESET(SPI5_R, RCC_SPI5CFGR, 0, 0),
53 RESET(SPI6_R, RCC_SPI6CFGR, 0, 0),
54 RESET(SPI7_R, RCC_SPI7CFGR, 0, 0),
55 RESET(SPI8_R, RCC_SPI8CFGR, 0, 0),
56 RESET(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),
57 RESET(USART1_R, RCC_USART1CFGR, 0, 0),
58 RESET(USART2_R, RCC_USART2CFGR, 0, 0),
59 RESET(USART3_R, RCC_USART3CFGR, 0, 0),
60 RESET(UART4_R, RCC_UART4CFGR, 0, 0),
61 RESET(UART5_R, RCC_UART5CFGR, 0, 0),
62 RESET(USART6_R, RCC_USART6CFGR, 0, 0),
63 RESET(UART7_R, RCC_UART7CFGR, 0, 0),
64 RESET(UART8_R, RCC_UART8CFGR, 0, 0),
65 RESET(UART9_R, RCC_UART9CFGR, 0, 0),
66 RESET(LPUART1_R, RCC_LPUART1CFGR, 0, 0),
67 RESET(IS2M_R, RCC_IS2MCFGR, 0, 0),
68 RESET(I2C1_R, RCC_I2C1CFGR, 0, 0),
69 RESET(I2C2_R, RCC_I2C2CFGR, 0, 0),
70 RESET(I2C3_R, RCC_I2C3CFGR, 0, 0),
71 RESET(I2C4_R, RCC_I2C4CFGR, 0, 0),
72 RESET(I2C5_R, RCC_I2C5CFGR, 0, 0),
73 RESET(I2C6_R, RCC_I2C6CFGR, 0, 0),
74 RESET(I2C7_R, RCC_I2C7CFGR, 0, 0),
75 RESET(I2C8_R, RCC_I2C8CFGR, 0, 0),
76 RESET(SAI1_R, RCC_SAI1CFGR, 0, 0),
77 RESET(SAI2_R, RCC_SAI2CFGR, 0, 0),
78 RESET(SAI3_R, RCC_SAI3CFGR, 0, 0),
79 RESET(SAI4_R, RCC_SAI4CFGR, 0, 0),
80 RESET(MDF1_R, RCC_MDF1CFGR, 0, 0),
81 RESET(MDF2_R, RCC_ADF1CFGR, 0, 0),
82 RESET(FDCAN_R, RCC_FDCANCFGR, 0, 0),
83 RESET(HDP_R, RCC_HDPCFGR, 0, 0),
84 RESET(ADC12_R, RCC_ADC12CFGR, 0, 0),
85 RESET(ADC3_R, RCC_ADC3CFGR, 0, 0),
86 RESET(ETH1_R, RCC_ETH1CFGR, 0, 0),
87 RESET(ETH2_R, RCC_ETH2CFGR, 0, 0),
88 RESET(USBH_R, RCC_USBHCFGR, 0, 0),
89 RESET(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),
90 RESET(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),
91 RESET(USB3DR_R, RCC_USB3DRCFGR, 0, 0),
92 RESET(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0, 0),
93 RESET(USBTC_R, RCC_UCPDCFGR, 0, 0),
94 RESET(ETHSW_R, RCC_ETHSWCFGR, 0, 0),
95 RESET(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),
96 RESET(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),
97 RESET(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),
98 RESET(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),
99 RESET(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),
100 RESET(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),
101 RESET(GPU_R, RCC_GPUCFGR, 0, 0),
102 RESET(LTDC_R, RCC_LTDCCFGR, 0, 0),
103 RESET(DSI_R, RCC_DSICFGR, 0, 0),
104 RESET(LVDS_R, RCC_LVDSCFGR, 0, 0),
105 RESET(CSI_R, RCC_CSICFGR, 0, 0),
106 RESET(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),
107 RESET(CCI_R, RCC_CCICFGR, 0, 0),
108 RESET(VDEC_R, RCC_VDECCFGR, 0, 0),
109 RESET(VENC_R, RCC_VENCCFGR, 0, 0),
110 RESET(WWDG1_R, RCC_WWDG1CFGR, 0, 0),
111 RESET(WWDG2_R, RCC_WWDG2CFGR, 0, 0),
112 RESET(VREF_R, RCC_VREFCFGR, 0, 0),
113 RESET(DTS_R, RCC_DTSCFGR, 0, 0),
114 RESET(CRC_R, RCC_CRCCFGR, 0, 0),
115 RESET(SERC_R, RCC_SERCCFGR, 0, 0),
116 RESET(OSPIIOM_R, RCC_OSPIIOMCFGR, 0, 0),
117 RESET(I3C1_R, RCC_I3C1CFGR, 0, 0),
118 RESET(I3C2_R, RCC_I3C2CFGR, 0, 0),
119 RESET(I3C3_R, RCC_I3C3CFGR, 0, 0),
120 RESET(I3C4_R, RCC_I3C4CFGR, 0, 0),
121 RESET(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),
122 RESET(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),
123 RESET(RNG_R, RCC_RNGCFGR, 0, 0),
124 RESET(PKA_R, RCC_PKACFGR, 0, 0),
125 RESET(SAES_R, RCC_SAESCFGR, 0, 0),
126 RESET(HASH_R, RCC_HASHCFGR, 0, 0),
127 RESET(CRYP1_R, RCC_CRYP1CFGR, 0, 0),
128 RESET(CRYP2_R, RCC_CRYP2CFGR, 0, 0),
129 RESET(PCIE_R, RCC_PCIECFGR, 0, 0),
130};
131
132static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl)
133{
134 unsigned long id = reset_ctl->id;
135
136 if (id < STM32MP25_LAST_RESET)
137 return stm32mp25_reset[id];
138
139 return NULL;
140}
141
142static const struct stm32_reset_data stm32mp25_reset_data = {
143 .get_reset_line = stm32_get_reset_line,
144 .clear_offset = RCC_CLR_OFFSET,
145 .reset_us = STM32_DEASSERT_TIMEOUT_US,
146};
147
148static int stm32_reset_probe(struct udevice *dev)
149{
150 return stm32_reset_core_probe(dev, &stm32mp25_reset_data);
151}
152
153U_BOOT_DRIVER(stm32mp25_rcc_reset) = {
154 .name = "stm32mp25_reset",
155 .id = UCLASS_RESET,
156 .probe = stm32_reset_probe,
157 .priv_auto = sizeof(struct stm32_reset_priv),
158 .ops = &stm32_reset_ops,
159};