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git01.mediatek.com / filogic / uboot / 53a7e98bb7c18da01a84bdfaa5525b9929b973a4 / . / drivers / clk / imx / clk-imx6ul.c
blob: 32fb949ffbcced2c376556921ce4a45bfca80464 [file] [log] [blame]
Michael Trimarchi93f55b72025-05-30 17:16:43 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2025 Amarula Solutions Software Engineering
4 * Michael Trimarchi, Amarula Solutions Software Engineering, michael@amarulasolutions.com
5 */
6
7#include <clk-uclass.h>
8#include <dm.h>
9#include <log.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <dt-bindings/clock/imx6ul-clock.h>
13
14#include "clk.h"
15
16static int imx6ul_clk_request(struct clk *clk)
17{
18 debug("%s: request clk id %ld\n", __func__, clk->id);
19
20 if (clk->id < IMX6UL_CLK_DUMMY || clk->id >= IMX6UL_CLK_END) {
21 printf("%s: Invalid clk ID #%lu\n", __func__, clk->id);
22 return -EINVAL;
23 }
24
25 return 0;
26}
27
28static struct clk_ops imx6ul_clk_ops = {
29 .request = imx6ul_clk_request,
30 .set_rate = ccf_clk_set_rate,
31 .get_rate = ccf_clk_get_rate,
32 .enable = ccf_clk_enable,
33 .disable = ccf_clk_disable,
34};
35
36static const char *const pll_bypass_src_sels[] = { "osc", "dummy", };
37static const char *const pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
38static const char *const bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
39static const char *const gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
40
41static const char *const enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m",
42 "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
43static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
44static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
45static const char *const periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m",
46 "pll4_audio_div", };
47static const char *const periph_clk2_sels[] = { "pll3_usb_otg", "osc", "pll2_bypass_src", };
48static const char *const periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
49static const char *const perclk_sels[] = { "ipg", "osc", };
50
51static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m",
52 "pll2_198m", };
53static const char *const uart_sels[] = { "pll3_80m", "osc", };
54static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
55
56static int imx6ul_clk_probe(struct udevice *dev)
57{
58 struct clk osc_clk;
59 void *base;
60 int ret;
61
62 /* Anatop clocks */
63 base = (void *)ANATOP_BASE_ADDR;
64
65 clk_dm(IMX6UL_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
66
67 ret = clk_get_by_name(dev, "osc", &osc_clk);
68 if (ret)
69 return ret;
70
71 clk_dm(IMX6UL_CLK_OSC, dev_get_clk_ptr(osc_clk.dev));
72
73 clk_dm(IMX6UL_CLK_PLL2,
74 imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
75 base + 0x30, 0x1));
76 clk_dm(IMX6UL_CLK_PLL3,
77 imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", "osc",
78 base + 0x10, 0x3));
79 clk_dm(IMX6UL_PLL3_BYPASS_SRC,
80 imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 1,
81 pll_bypass_src_sels,
82 ARRAY_SIZE(pll_bypass_src_sels)));
83 clk_dm(IMX6UL_PLL3_BYPASS,
84 imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
85 pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels),
86 CLK_SET_RATE_PARENT));
87 clk_dm(IMX6UL_CLK_PLL3_USB_OTG,
88 imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10,
89 13));
90 clk_dm(IMX6UL_CLK_PLL3_80M,
91 imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6));
92 clk_dm(IMX6UL_CLK_PLL3_60M,
93 imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8));
94 clk_dm(IMX6UL_CLK_PLL2_PFD0,
95 imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
96 clk_dm(IMX6UL_CLK_PLL2_PFD1,
97 imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1));
98 clk_dm(IMX6UL_CLK_PLL2_PFD2,
99 imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
100 clk_dm(IMX6UL_CLK_PLL2_PFD3,
101 imx_clk_pfd("pll2_pfd3_396m", "pll2_bus", base + 0x100, 3));
102 clk_dm(IMX6UL_CLK_PLL6,
103 imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0,
104 0x3));
105 clk_dm(IMX6UL_CLK_PLL6_ENET,
106 imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
107
108 /* CCM clocks */
109 base = dev_read_addr_ptr(dev);
110 if (!base)
111 return -EINVAL;
112
113 clk_dm(IMX6UL_CLK_GPMI_SEL,
114 imx_clk_mux(dev, "gpmi_sel", base + 0x1c, 19, 1, gpmi_sels,
115 ARRAY_SIZE(gpmi_sels)));
116 clk_dm(IMX6UL_CLK_BCH_SEL,
117 imx_clk_mux(dev, "bch_sel", base + 0x1c, 18, 1, bch_sels,
118 ARRAY_SIZE(bch_sels)));
119 clk_dm(IMX6UL_CLK_USDHC1_SEL,
120 imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,
121 ARRAY_SIZE(usdhc_sels)));
122 clk_dm(IMX6UL_CLK_USDHC2_SEL,
123 imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,
124 ARRAY_SIZE(usdhc_sels)));
125 clk_dm(IMX6UL_CLK_ECSPI_SEL,
126 imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
127 ARRAY_SIZE(ecspi_sels)));
128 clk_dm(IMX6UL_CLK_UART_SEL,
129 imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels,
130 ARRAY_SIZE(uart_sels)));
131 clk_dm(IMX6UL_CLK_ENFC_SEL,
132 imx_clk_mux(dev, "enfc_sel", base + 0x2c, 15, 3, enfc_sels,
133 ARRAY_SIZE(enfc_sels)));
134 clk_dm(IMX6UL_CLK_PERCLK_SEL,
135 imx_clk_mux(dev, "perclk_sel", base + 0x1c, 6, 1, perclk_sels,
136 ARRAY_SIZE(perclk_sels)));
137 clk_dm(IMX6UL_CLK_PERIPH_PRE,
138 imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2,
139 periph_pre_sels, ARRAY_SIZE(periph_pre_sels)));
140 clk_dm(IMX6UL_CLK_PERIPH2_PRE,
141 imx_clk_mux(dev, "periph2_pre", base + 0x18, 21, 2,
142 periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)));
143 clk_dm(IMX6UL_CLK_PERIPH_CLK2_SEL,
144 imx_clk_mux(dev, "periph_clk2_sel", base + 0x18, 12, 2,
145 periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)));
146 clk_dm(IMX6UL_CLK_PERIPH2_CLK2_SEL,
147 imx_clk_mux(dev, "periph2_clk2_sel", base + 0x18, 20, 1,
148 periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)));
149 clk_dm(IMX6UL_CLK_PERIPH,
150 imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48,
151 5, periph_sels, ARRAY_SIZE(periph_sels)));
152 clk_dm(IMX6UL_CLK_AHB,
153 imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3,
154 base + 0x48, 1));
155 clk_dm(IMX6UL_CLK_PERIPH_CLK2,
156 imx_clk_divider(dev, "periph_clk2", "periph_clk2_sel",
157 base + 0x14, 27, 3));
158 clk_dm(IMX6UL_CLK_PERIPH2_CLK2,
159 imx_clk_divider(dev, "periph2_clk2", "periph2_clk2_sel",
160 base + 0x14, 0, 3));
161 clk_dm(IMX6UL_CLK_IPG,
162 imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2));
163 clk_dm(IMX6UL_CLK_ENFC_PRED,
164 imx_clk_divider(dev, "enfc_pred", "enfc_sel", base + 0x2c, 18,
165 3));
166 clk_dm(IMX6UL_CLK_ENFC_PODF,
167 imx_clk_divider(dev, "enfc_podf", "enfc_pred", base + 0x2c, 21,
168 6));
169 clk_dm(IMX6UL_CLK_GPMI_PODF,
170 imx_clk_divider(dev, "gpmi_podf", "gpmi_sel", base + 0x24, 22,
171 3));
172 clk_dm(IMX6UL_CLK_BCH_PODF,
173 imx_clk_divider(dev, "bch_podf", "bch_sel", base + 0x24, 19, 3));
174 clk_dm(IMX6UL_CLK_PERCLK,
175 imx_clk_divider(dev, "perclk", "perclk_sel", base + 0x1c, 0, 6));
176 clk_dm(IMX6UL_CLK_UART_PODF,
177 imx_clk_divider(dev, "uart_podf", "uart_sel", base + 0x24, 0,
178 6));
179 clk_dm(IMX6UL_CLK_USDHC1_PODF,
180 imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24,
181 11, 3));
182 clk_dm(IMX6UL_CLK_USDHC2_PODF,
183 imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24,
184 16, 3));
185 clk_dm(IMX6UL_CLK_ECSPI_PODF,
186 imx_clk_divider(dev, "ecspi_podf", "ecspi_sel", base + 0x38, 19,
187 6));
188
189 clk_dm(IMX6UL_CLK_APBHDMA,
190 imx_clk_gate2(dev, "apbh_dma", "bch_podf", base + 0x68, 4));
191 clk_dm(IMX6UL_CLK_ECSPI1,
192 imx_clk_gate2(dev, "ecspi1", "ecspi_podf", base + 0x6c, 0));
193 clk_dm(IMX6UL_CLK_ECSPI2,
194 imx_clk_gate2(dev, "ecspi2", "ecspi_podf", base + 0x6c, 2));
195 clk_dm(IMX6UL_CLK_ECSPI3,
196 imx_clk_gate2(dev, "ecspi3", "ecspi_podf", base + 0x6c, 4));
197 clk_dm(IMX6UL_CLK_ECSPI4,
198 imx_clk_gate2(dev, "ecspi4", "ecspi_podf", base + 0x6c, 6));
199
200 clk_dm(IMX6UL_CLK_USBOH3,
201 imx_clk_gate2(dev, "usboh3", "ipg", base + 0x80, 0));
202 clk_dm(IMX6UL_CLK_USDHC1,
203 imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
204 clk_dm(IMX6UL_CLK_USDHC2,
205 imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
206
207 clk_dm(IMX6UL_CLK_UART1_IPG,
208 imx_clk_gate2(dev, "uart1_ipg", "ipg", base + 0x7c, 24));
209 clk_dm(IMX6UL_CLK_UART1_SERIAL,
210 imx_clk_gate2(dev, "uart1_serial", "uart_podf", base + 0x7c, 24));
211 clk_dm(IMX6UL_CLK_UART2_IPG,
212 imx_clk_gate2(dev, "uart2_ipg", "ipg", base + 0x68, 28));
213 clk_dm(IMX6UL_CLK_UART2_SERIAL,
214 imx_clk_gate2(dev, "uart2_serial", "uart_podf", base + 0x68, 28));
215 clk_dm(IMX6UL_CLK_UART3_IPG,
216 imx_clk_gate2(dev, "uart3_ipg", "ipg", base + 0x6c, 10));
217 clk_dm(IMX6UL_CLK_UART3_SERIAL,
218 imx_clk_gate2(dev, "uart3_serial", "uart_podf", base + 0x6c, 10));
219 clk_dm(IMX6UL_CLK_UART4_IPG,
220 imx_clk_gate2(dev, "uart4_ipg", "ipg", base + 0x6c, 24));
221 clk_dm(IMX6UL_CLK_UART4_SERIAL,
222 imx_clk_gate2(dev, "uart4_serial", "uart_podf", base + 0x6c, 24));
223 clk_dm(IMX6UL_CLK_UART5_IPG,
224 imx_clk_gate2(dev, "uart5_ipg", "ipg", base + 0x74, 2));
225 clk_dm(IMX6UL_CLK_UART5_SERIAL,
226 imx_clk_gate2(dev, "uart5_serial", "uart_podf", base + 0x74, 2));
227 clk_dm(IMX6UL_CLK_UART6_IPG,
228 imx_clk_gate2(dev, "uart6_ipg", "ipg", base + 0x74, 6));
229 clk_dm(IMX6UL_CLK_UART6_SERIAL,
230 imx_clk_gate2(dev, "uart6_serial", "uart_podf", base + 0x74, 6));
231 clk_dm(IMX6UL_CLK_UART7_IPG,
232 imx_clk_gate2(dev, "uart7_ipg", "ipg", base + 0x7c, 26));
233 clk_dm(IMX6UL_CLK_UART7_SERIAL,
234 imx_clk_gate2(dev, "uart7_serial", "uart_podf", base + 0x7c, 26));
235 clk_dm(IMX6UL_CLK_UART8_IPG,
236 imx_clk_gate2(dev, "uart8_ipg", "ipg", base + 0x80, 14));
237 clk_dm(IMX6UL_CLK_UART8_SERIAL,
238 imx_clk_gate2(dev, "uart8_serial", "uart_podf", base + 0x80, 14));
239
240#if CONFIG_IS_ENABLED(NAND_MXS)
241 clk_dm(IMX6UL_CLK_PER_BCH,
242 imx_clk_gate2(dev, "per_bch", "bch_podf", base + 0x78, 12));
243 clk_dm(IMX6UL_CLK_GPMI_BCH_APB,
244 imx_clk_gate2(dev, "gpmi_bch_apb", "bch_podf", base + 0x78, 24));
245 clk_dm(IMX6UL_CLK_GPMI_BCH,
246 imx_clk_gate2(dev, "gpmi_bch", "gpmi_podf", base + 0x78, 26));
247 clk_dm(IMX6UL_CLK_GPMI_IO,
248 imx_clk_gate2(dev, "gpmi_io", "enfc_podf", base + 0x78, 28));
249 clk_dm(IMX6UL_CLK_GPMI_APB,
250 imx_clk_gate2(dev, "gpmi_apb", "bch_podf", base + 0x78, 30));
251#endif
252
253 clk_dm(IMX6UL_CLK_I2C1,
254 imx_clk_gate2(dev, "i2c1", "perclk", base + 0x70, 6));
255 clk_dm(IMX6UL_CLK_I2C2,
256 imx_clk_gate2(dev, "i2c2", "perclk", base + 0x70, 8));
257 clk_dm(IMX6UL_CLK_I2C3,
258 imx_clk_gate2(dev, "i2c3", "perclk", base + 0x70, 10));
259 clk_dm(IMX6UL_CLK_PWM1,
260 imx_clk_gate2(dev, "pwm1", "perclk", base + 0x78, 16));
261
262 clk_dm(IMX6UL_CLK_ENET,
263 imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
264 clk_dm(IMX6UL_CLK_ENET_REF,
265 imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1));
266
267 struct clk *clk, *clk1;
268
269 clk_get_by_id(IMX6UL_CLK_ENFC_SEL, &clk);
270 clk_get_by_id(IMX6UL_CLK_PLL2_PFD2, &clk1);
271
272 clk_set_parent(clk, clk1);
273
274 return 0;
275}
276
277static const struct udevice_id imx6ul_clk_ids[] = {
278 { .compatible = "fsl,imx6ul-ccm" },
279 { },
280};
281
282U_BOOT_DRIVER(imx6ul_clk) = {
283 .name = "clk_imx6ul",
284 .id = UCLASS_CLK,
285 .of_match = imx6ul_clk_ids,
286 .ops = &imx6ul_clk_ops,
287 .probe = imx6ul_clk_probe,
288 .flags = DM_FLAG_PRE_RELOC,
289};