| Michal Simek | 952d514 | 2007-03-11 13:42:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 Michal Simek |
| 3 | * |
| 4 | * Michal SIMEK <monstr@monstr.eu> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | .text |
| 25 | .globl dcache_enable |
| 26 | .ent dcache_enable |
| 27 | .align 2 |
| 28 | dcache_enable: |
| 29 | /* Make space on stack for a temporary */ |
| 30 | addi r1, r1, -4 |
| 31 | /* Save register r12 */ |
| 32 | swi r12, r1, 0 |
| 33 | /* Read the MSR register */ |
| 34 | mfs r12, rmsr |
| 35 | /* Set the instruction enable bit */ |
| 36 | ori r12, r12, 0x80 |
| 37 | /* Save the MSR register */ |
| 38 | mts rmsr, r12 |
| 39 | /* Load register r12 */ |
| 40 | lwi r12, r1, 0 |
| 41 | /* Return */ |
| 42 | rtsd r15, 8 |
| 43 | /* Update stack in the delay slot */ |
| 44 | addi r1, r1, 4 |
| 45 | .end dcache_enable |
| 46 | |
| 47 | .text |
| 48 | .globl dcache_disable |
| 49 | .ent dcache_disable |
| 50 | .align 2 |
| 51 | dcache_disable: |
| 52 | /* Make space on stack for a temporary */ |
| 53 | addi r1, r1, -4 |
| 54 | /* Save register r12 */ |
| 55 | swi r12, r1, 0 |
| 56 | /* Read the MSR register */ |
| 57 | mfs r12, rmsr |
| 58 | /* Clear the data cache enable bit */ |
| 59 | andi r12, r12, ~0x80 |
| 60 | /* Save the MSR register */ |
| 61 | mts rmsr, r12 |
| 62 | /* Load register r12 */ |
| 63 | lwi r12, r1, 0 |
| 64 | /* Return */ |
| 65 | rtsd r15, 8 |
| 66 | /* Update stack in the delay slot */ |
| 67 | addi r1, r1, 4 |
| 68 | .end dcache_disable |