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Markus Klotzbuecher8f824852006-07-12 08:48:24 +02001/*
2 * (C) Copyright 2006
3 * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
4 *
5 * Configuation settings for the SPC1920 board.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __H
24#define __CONFIG_H
25
26#define CONFIG_SPC1920 1 /* SPC1920 board */
27#define CONFIG_MPC885 1 /* MPC885 CPU */
28
29#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
30#undef CONFIG_8xx_CONS_SMC2
31#undef CONFIG_8xx_CONS_NONE
32
33#define CONFIG_MII
34/* #define MII_DEBUG */
35/* #define CONFIG_FEC_ENET */
36#undef CONFIG_ETHER_ON_FEC1
37#define CONFIG_ETHER_ON_FEC2
38#define FEC_ENET
39/* #define CONFIG_FEC2_PHY_NORXERR */
40/* #define CFG_DISCOVER_PHY */
41/* #define CONFIG_PHY_ADDR 0x1 */
42#define CONFIG_FEC2_PHY 1
43
44#define CONFIG_BAUDRATE 19200
45
46/* use PLD CLK4 instead of brg */
Markus Klotzbuechercf7bf182007-01-09 14:57:11 +010047#define CFG_SPC1920_SMC1_CLK4
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020048
49#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
50#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
51#define CFG_8xx_CPUCLK_MIN 40000000
52#define CFG_8xx_CPUCLK_MAX 133000000
53
Markus Klotzbuecher63ee6fe2007-01-09 14:57:13 +010054#define CFG_RESET_ADDRESS 0xC0000000
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020055
56#define CONFIG_BOARD_EARLY_INIT_F
Markus Klotzbuecher63ee6fe2007-01-09 14:57:13 +010057#define CONFIG_LAST_STAGE_INIT
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020058
Markus Klotzbuecher63ee6fe2007-01-09 14:57:13 +010059#if 0
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020060#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
61#else
62#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
63#endif
64
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_NFSBOOTCOMMAND \
68 "dhcp;" \
69 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
70 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
71 "bootm"
72
73#define CONFIG_BOOTCOMMAND \
74 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
75 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
76 "bootm fe080000"
77
78#undef CONFIG_BOOTARGS
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
82
83#ifndef CONFIG_COMMANDS
84#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
85 | CFG_CMD_ASKENV \
Markus Klotzbuecher837d2fd2007-01-09 14:57:12 +010086 | CFG_CMD_DATE \
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020087 | CFG_CMD_ECHO \
88 | CFG_CMD_IMMAP \
89 | CFG_CMD_JFFS2 \
90 | CFG_CMD_PING \
91 | CFG_CMD_DHCP \
Markus Klotzbuecherce6f3182007-01-09 14:57:10 +010092 | CFG_CMD_I2C \
Markus Klotzbuecher8f824852006-07-12 08:48:24 +020093 | CFG_CMD_MII)
94 /* & ~( CFG_CMD_NET)) */
95
96
97#endif /* !CONFIG_COMMANDS */
98
99/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
100#include <cmd_confdefs.h>
101
102/*
103 * Miscellaneous configurable options
104 */
105#define CFG_LONGHELP /* undef to save memory */
106#define CFG_PROMPT "=>" /* Monitor Command Prompt */
107#define CFG_HUSH_PARSER
108#define CFG_PROMPT_HUSH_PS2 "> "
109
110#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
111#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
112#else
113#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
114#endif
115
116#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
117#define CFG_MAXARGS 16 /* max number of command args */
118#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119
120#define CFG_LOAD_ADDR 0x00100000
121
122#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
123
124#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
125
126/*
127 * Low Level Configuration Settings
128 * (address mappings, register initial values, etc.)
129 * You should know what you are doing if you make changes here.
130 */
131
132/*-----------------------------------------------------------------------
133 * Internal Memory Mapped Register
134 */
135#define CFG_IMMR 0xF0000000
136
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area (in DPRAM)
139 */
140#define CFG_INIT_RAM_ADDR CFG_IMMR
141#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
142#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
143#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
144#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
145
146/*-----------------------------------------------------------------------
147 * Start addresses for the final memory configuration
148 * (Set up by the startup code)
149 * Please note that CFG_SDRAM_BASE _must_ start at 0
150 */
151#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
152#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
153
154/*
155 * For booting Linux, the board info and command line data
156 * have to be in the first 8 MB of memory, since this is
157 * the maximum mapped by the Linux kernel during initialization.
158 */
159#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
160
161#define CFG_MONITOR_BASE TEXT_BASE
162#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
163
164#ifdef CONFIG_BZIP2
165#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
166#else
167#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
168#endif /* CONFIG_BZIP2 */
169
170#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
171
172/*
173 * Flash
174 */
175/*-----------------------------------------------------------------------
176 * Flash organisation
177 */
178#define CFG_FLASH_BASE 0xFE000000
179#define CFG_FLASH_CFI /* The flash is CFI compatible */
180#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
181#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
182#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
183
184/* Environment is in flash */
185#define CFG_ENV_IS_IN_FLASH
186#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
187#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
188
189#define CONFIG_ENV_OVERWRITE
190
191/*-----------------------------------------------------------------------
192 * Cache Configuration
193 */
194#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
196
Markus Klotzbuecher837d2fd2007-01-09 14:57:12 +0100197#ifdef CFG_CMD_DATE
198# define CONFIG_RTC_DS3231
199# define CFG_I2C_RTC_ADDR 0x68
200#endif
201
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200202/*-----------------------------------------------------------------------
203 * I2C configuration
204 */
205#if (CONFIG_COMMANDS & CFG_CMD_I2C)
Markus Klotzbuecher2df462d2007-01-09 14:57:10 +0100206/* enable I2C and select the hardware/software driver */
207#undef CONFIG_HARD_I2C /* I2C with hardware support */
208#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
209
210#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
211#define CFG_I2C_SLAVE 0xFE
212
213#ifdef CONFIG_SOFT_I2C
214/*
215 * Software (bit-bang) I2C driver configuration
216 */
217#define PB_SCL 0x00000020 /* PB 26 */
218#define PB_SDA 0x00000010 /* PB 27 */
219
220#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
221#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
222#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
223#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
224#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
Markus Klotzbuecherce6f3182007-01-09 14:57:10 +0100225 else immr->im_cpm.cp_pbdat &= ~PB_SDA
Markus Klotzbuecher2df462d2007-01-09 14:57:10 +0100226#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
Markus Klotzbuecherce6f3182007-01-09 14:57:10 +0100227 else immr->im_cpm.cp_pbdat &= ~PB_SCL
Markus Klotzbuecher2df462d2007-01-09 14:57:10 +0100228#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
229#endif /* CONFIG_SOFT_I2C */
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200230#endif
231
232/*-----------------------------------------------------------------------
233 * SYPCR - System Protection Control 11-9
234 * SYPCR can only be written once after reset!
235 *-----------------------------------------------------------------------
236 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
237 */
238#if defined(CONFIG_WATCHDOG)
239#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
240 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
241#else
242#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
243#endif
244
245/*-----------------------------------------------------------------------
246 * SIUMCR - SIU Module Configuration 11-6
247 *-----------------------------------------------------------------------
248 * PCMCIA config., multi-function pin tri-state
249 */
Markus Klotzbuecher63ee6fe2007-01-09 14:57:13 +0100250#define CFG_SIUMCR (SIUMCR_FRC)
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200251
252/*-----------------------------------------------------------------------
253 * TBSCR - Time Base Status and Control 11-26
254 *-----------------------------------------------------------------------
255 * Clear Reference Interrupt Status, Timebase freezing enabled
256 */
257#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
258
259/*-----------------------------------------------------------------------
260 * PISCR - Periodic Interrupt Status and Control 11-31
261 *-----------------------------------------------------------------------
262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
263 */
264#define CFG_PISCR (PISCR_PS | PISCR_PITF)
265
266/*-----------------------------------------------------------------------
267 * SCCR - System Clock and reset Control Register 15-27
268 *-----------------------------------------------------------------------
269 * Set clock output, timebase and RTC source and divider,
270 * power management and some other internal clocks
271 */
272#define SCCR_MASK SCCR_EBDF11
273/* #define CFG_SCCR SCCR_TBS */
274#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
276 SCCR_DFALCD00)
277
278/*-----------------------------------------------------------------------
279 * DER - Debug Enable Register
280 *-----------------------------------------------------------------------
281 * Set to zero to prevent the processor from entering debug mode
282 */
283#define CFG_DER 0
284
285
286/* Because of the way the 860 starts up and assigns CS0 the entire
287 * address space, we have to set the memory controller differently.
288 * Normally, you write the option register first, and then enable the
289 * chip select by writing the base register. For CS0, you must write
290 * the base register first, followed by the option register.
291 */
292
293
294/*
295 * Init Memory Controller:
296 */
297
298/* BR0 and OR0 (FLASH) */
299#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
300
301
302/* used to re-map FLASH both when starting from SRAM or FLASH:
303 * restrict access enough to keep SRAM working (if any)
304 * but not too much to meddle with FLASH accesses
305 */
306#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
307#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
308
309/*
310 * FLASH timing:
311 */
312#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
Markus Klotzbuecher08f7bde2007-01-09 14:57:14 +0100313 OR_SCY_6_CLK | OR_EHTR | OR_BI)
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200314
315#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
316#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
317#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
318
319
320/*
321 * SDRAM CS1 UPMB
322 */
323#define CFG_SDRAM_BASE 0x00000000
324#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
325#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
326
327#define CFG_PRELIM_OR1_AM 0xF0000000
328/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
329#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
330
331#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
332#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
333
334/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
335/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
336
337#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
338#define CFG_PTA_PER_CLK 195
339#define CFG_MBMR_PTB 195
340#define CFG_MPTPR MPTPR_PTP_DIV16
341#define CFG_MAR 0x88
342
343#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
344 MBMR_AMB_TYPE_0 | \
345 MBMR_G0CLB_A10 | \
346 MBMR_DSB_1_CYCL | \
347 MBMR_RLFB_1X | \
348 MBMR_WLFB_1X | \
349 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
350
351#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
352 MBMR_AMB_TYPE_1 | \
353 MBMR_G0CLB_A10 | \
354 MBMR_DSB_1_CYCL | \
355 MBMR_RLFB_1X | \
356 MBMR_WLFB_1X | \
357 MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
358
359
Markus Klotzbuecher0dda6452007-01-09 14:57:10 +0100360/*
361 * DSP Host Port Interface CS3
362 */
363#define CFG_SPC1920_HPI_BASE 0x90000000
Markus Klotzbuecher79bac7a2007-01-09 16:02:48 +0100364#define CFG_PRELIM_OR3_AM 0xF8000000
Markus Klotzbuecher0dda6452007-01-09 14:57:10 +0100365
Markus Klotzbuecher79bac7a2007-01-09 16:02:48 +0100366#define CFG_OR3 (CFG_PRELIM_OR3_AM | \
Markus Klotzbuecher0dda6452007-01-09 14:57:10 +0100367 OR_G5LS | \
368 OR_SCY_0_CLK | \
369 OR_BI)
370
Markus Klotzbuecher79bac7a2007-01-09 16:02:48 +0100371#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
Markus Klotzbuecher0dda6452007-01-09 14:57:10 +0100372 BR_MS_UPMA | \
373 BR_PS_16 | \
374 BR_V);
375
376#define CFG_MAMR (MAMR_GPL_A4DIS | \
377 MAMR_RLFA_5X | \
378 MAMR_WLFA_5X)
379
380#define CONFIG_SPC1920_HPI_TEST
381
382#ifdef CONFIG_SPC1920_HPI_TEST
383#define HPI_REG(x) (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
384#define HPI_HPIC_1 HPI_REG(0)
385#define HPI_HPIC_2 HPI_REG(2)
Markus Klotzbuecherfa11c672007-01-09 14:57:13 +0100386#define HPI_HPIA_1 HPI_REG(0x2000008)
387#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
388#define HPI_HPID_INC_1 HPI_REG(0x1000004)
389#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
390#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
391#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
Markus Klotzbuecher0dda6452007-01-09 14:57:10 +0100392#endif /* CONFIG_SPC1920_HPI_TEST */
393
Markus Klotzbuecherce6f3182007-01-09 14:57:10 +0100394/*
Markus Klotzbuecherce2746d2007-01-09 14:57:13 +0100395 * Ramtron FM18L08 FRAM 32KB on CS4
396 */
397#define CFG_SPC1920_FRAM_BASE 0x80100000
398#define CFG_PRELIM_OR4_AM 0xffff8000
Markus Klotzbuecher79bac7a2007-01-09 16:02:48 +0100399#define CFG_OR4 (CFG_PRELIM_OR4_AM | \
Markus Klotzbuecherce2746d2007-01-09 14:57:13 +0100400 OR_ACS_DIV2 | \
401 OR_BI | \
402 OR_SCY_4_CLK | \
403 OR_TRLX)
404
Markus Klotzbuecher79bac7a2007-01-09 16:02:48 +0100405#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
Markus Klotzbuecherce2746d2007-01-09 14:57:13 +0100406
407/*
Markus Klotzbuecher63ee6fe2007-01-09 14:57:13 +0100408 * PLD CS5
Markus Klotzbuecherce6f3182007-01-09 14:57:10 +0100409 */
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200410#define CFG_SPC1920_PLD_BASE 0x80000000
Markus Klotzbuecherce2746d2007-01-09 14:57:13 +0100411#define CFG_PRELIM_OR5_AM 0xffff8000
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200412
413#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
414 OR_CSNT_SAM | \
415 OR_ACS_DIV1 | \
416 OR_BI | \
417 OR_SCY_0_CLK | \
418 OR_TRLX)
419
420#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
421
Markus Klotzbuecher8f824852006-07-12 08:48:24 +0200422/*
423 * Internal Definitions
424 *
425 * Boot Flags
426 */
427#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
428#define BOOTFLAG_WARM 0x02 /* Software reboot */
429
430/* Machine type
431*/
432#define _MACH_8xx (_MACH_fads)
433
434#endif /* __CONFIG_H */