blob: 894975f3fe9506de106141fcfe94d5a501d860b5 [file] [log] [blame]
Kever Yang536dea82017-11-03 15:16:12 +08001/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <sysreset.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/cru_rk3328.h>
14#include <asm/arch/hardware.h>
15#include <linux/err.h>
16
17int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
18{
19 struct sysreset_reg *offset = dev_get_priv(dev);
20 unsigned long cru_base = (unsigned long)rockchip_get_cru();
21
22 if (IS_ERR_VALUE(cru_base))
23 return (int)cru_base;
24
25 switch (type) {
26 case SYSRESET_WARM:
27 writel(0xeca8, cru_base + offset->glb_srst_snd_value);
28 break;
29 case SYSRESET_COLD:
30 writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
31 break;
32 default:
33 return -EPROTONOSUPPORT;
34 }
35
36 return -EINPROGRESS;
37}
38
39static struct sysreset_ops rockchip_sysreset = {
40 .request = rockchip_sysreset_request,
41};
42
43U_BOOT_DRIVER(sysreset_rockchip) = {
44 .name = "rockchip_sysreset",
45 .id = UCLASS_SYSRESET,
46 .ops = &rockchip_sysreset,
47};