| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* Copyright (c) 2022 Microchip Technology Inc */ |
| 3 | |
| 4 | / { |
| 5 | fabric_clk3: fabric-clk3 { |
| 6 | compatible = "fixed-clock"; |
| 7 | #clock-cells = <0>; |
| 8 | clock-frequency = <62500000>; |
| 9 | }; |
| 10 | |
| 11 | fabric_clk1: fabric-clk1 { |
| 12 | compatible = "fixed-clock"; |
| 13 | #clock-cells = <0>; |
| 14 | clock-frequency = <125000000>; |
| 15 | }; |
| 16 | |
| 17 | pcie: pcie@2000000000 { |
| 18 | compatible = "microchip,pcie-host-1.0"; |
| 19 | #address-cells = <0x3>; |
| 20 | #interrupt-cells = <0x1>; |
| 21 | #size-cells = <0x2>; |
| 22 | device_type = "pci"; |
| 23 | reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; |
| 24 | reg-names = "cfg", "apb"; |
| 25 | bus-range = <0x0 0x7f>; |
| 26 | interrupt-parent = <&plic>; |
| 27 | interrupts = <119>; |
| 28 | interrupt-map = <0 0 0 1 &pcie_intc 0>, |
| 29 | <0 0 0 2 &pcie_intc 1>, |
| 30 | <0 0 0 3 &pcie_intc 2>, |
| 31 | <0 0 0 4 &pcie_intc 3>; |
| 32 | interrupt-map-mask = <0 0 0 7>; |
| 33 | clocks = <&fabric_clk1>, <&fabric_clk3>; |
| 34 | clock-names = "fic0", "fic3"; |
| 35 | ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; |
| 36 | msi-parent = <&pcie>; |
| 37 | msi-controller; |
| 38 | status = "disabled"; |
| 39 | pcie_intc: interrupt-controller { |
| 40 | #address-cells = <0>; |
| 41 | #interrupt-cells = <1>; |
| 42 | interrupt-controller; |
| 43 | }; |
| 44 | }; |
| 45 | }; |