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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / mips / ingenic / x1830.dtsi
blob: 65a5da71c1994726876d5106f865054bbe462dda [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/ingenic,tcu.h>
3#include <dt-bindings/clock/ingenic,x1830-cgu.h>
4#include <dt-bindings/dma/x1830-dma.h>
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,x1830";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
19
20 clocks = <&cgu X1830_CLK_CPU>;
21 clock-names = "cpu";
22 };
23 };
24
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
30 };
31
32 intc: interrupt-controller@10001000 {
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
34 reg = <0x10001000 0x50>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
38
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
41 };
42
43 exclk: ext {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 };
47
48 rtclk: rtc {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <32768>;
52 };
53
54 cgu: x1830-cgu@10000000 {
55 compatible = "ingenic,x1830-cgu", "simple-mfd";
56 reg = <0x10000000 0x100>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0x0 0x10000000 0x100>;
60
61 #clock-cells = <1>;
62
63 clocks = <&exclk>, <&rtclk>;
64 clock-names = "ext", "rtc";
65
66 otg_phy: usb-phy@3c {
67 compatible = "ingenic,x1830-phy";
68 reg = <0x3c 0x10>;
69
70 clocks = <&cgu X1830_CLK_OTGPHY>;
71
72 #phy-cells = <0>;
73
74 status = "disabled";
75 };
76
77 mac_phy_ctrl: mac-phy-ctrl@e8 {
78 compatible = "syscon";
79 reg = <0xe8 0x4>;
80 };
81 };
82
83 ost: timer@12000000 {
84 compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
85 reg = <0x12000000 0x3c>;
86
87 #clock-cells = <1>;
88
89 clocks = <&cgu X1830_CLK_OST>;
90 clock-names = "ost";
91
92 interrupt-parent = <&cpuintc>;
93 interrupts = <4>;
94 };
95
96 tcu: timer@10002000 {
97 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
98 reg = <0x10002000 0x1000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0x0 0x10002000 0x1000>;
102
103 #clock-cells = <1>;
104
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
109 clock-names = "rtc", "ext", "pclk", "tcu";
110
111 interrupt-controller;
112 #interrupt-cells = <1>;
113
114 interrupt-parent = <&intc>;
115 interrupts = <27 26 25>;
116
117 wdt: watchdog@0 {
118 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
119 reg = <0x0 0x10>;
120
121 clocks = <&tcu TCU_CLK_WDT>;
122 clock-names = "wdt";
123 };
124
125 pwm: pwm@40 {
126 compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
127 reg = <0x40 0x80>;
128
129 #pwm-cells = <3>;
130
131 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
132 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
133 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
134 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
135 clock-names = "timer0", "timer1", "timer2", "timer3",
136 "timer4", "timer5", "timer6", "timer7";
137 };
138 };
139
140 rtc: rtc@10003000 {
141 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
142 reg = <0x10003000 0x4c>;
143
144 interrupt-parent = <&intc>;
145 interrupts = <32>;
146
147 clocks = <&cgu X1830_CLK_RTCLK>;
148 clock-names = "rtc";
149 };
150
151 pinctrl: pin-controller@10010000 {
152 compatible = "ingenic,x1830-pinctrl";
153 reg = <0x10010000 0x800>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 gpa: gpio@0 {
158 compatible = "ingenic,x1830-gpio";
159 reg = <0>;
160
161 gpio-controller;
162 gpio-ranges = <&pinctrl 0 0 32>;
163 #gpio-cells = <2>;
164
165 interrupt-controller;
166 #interrupt-cells = <2>;
167
168 interrupt-parent = <&intc>;
169 interrupts = <17>;
170 };
171
172 gpb: gpio@1 {
173 compatible = "ingenic,x1830-gpio";
174 reg = <1>;
175
176 gpio-controller;
177 gpio-ranges = <&pinctrl 0 32 32>;
178 #gpio-cells = <2>;
179
180 interrupt-controller;
181 #interrupt-cells = <2>;
182
183 interrupt-parent = <&intc>;
184 interrupts = <16>;
185 };
186
187 gpc: gpio@2 {
188 compatible = "ingenic,x1830-gpio";
189 reg = <2>;
190
191 gpio-controller;
192 gpio-ranges = <&pinctrl 0 64 32>;
193 #gpio-cells = <2>;
194
195 interrupt-controller;
196 #interrupt-cells = <2>;
197
198 interrupt-parent = <&intc>;
199 interrupts = <15>;
200 };
201
202 gpd: gpio@3 {
203 compatible = "ingenic,x1830-gpio";
204 reg = <3>;
205
206 gpio-controller;
207 gpio-ranges = <&pinctrl 0 96 32>;
208 #gpio-cells = <2>;
209
210 interrupt-controller;
211 #interrupt-cells = <2>;
212
213 interrupt-parent = <&intc>;
214 interrupts = <14>;
215 };
216 };
217
218 uart0: serial@10030000 {
219 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
220 reg = <0x10030000 0x100>;
221
222 interrupt-parent = <&intc>;
223 interrupts = <51>;
224
225 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
226 clock-names = "baud", "module";
227
228 status = "disabled";
229 };
230
231 uart1: serial@10031000 {
232 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
233 reg = <0x10031000 0x100>;
234
235 interrupt-parent = <&intc>;
236 interrupts = <50>;
237
238 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
239 clock-names = "baud", "module";
240
241 status = "disabled";
242 };
243
244 ssi0: spi@10043000 {
245 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
246 reg = <0x10043000 0x20>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 interrupt-parent = <&intc>;
251 interrupts = <9>;
252
253 clocks = <&cgu X1830_CLK_SSI0>;
254 clock-names = "spi";
255
256 dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
257 <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
258 dma-names = "rx", "tx";
259
260 status = "disabled";
261 };
262
263 ssi1: spi@10044000 {
264 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
265 reg = <0x10044000 0x20>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268
269 interrupt-parent = <&intc>;
270 interrupts = <8>;
271
272 clocks = <&cgu X1830_CLK_SSI1>;
273 clock-names = "spi";
274
275 dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
276 <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
277 dma-names = "rx", "tx";
278
279 status = "disabled";
280 };
281
282 i2c0: i2c-controller@10050000 {
283 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
284 reg = <0x10050000 0x1000>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287
288 interrupt-parent = <&intc>;
289 interrupts = <60>;
290
291 clocks = <&cgu X1830_CLK_SMB0>;
292
293 status = "disabled";
294 };
295
296 i2c1: i2c-controller@10051000 {
297 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
298 reg = <0x10051000 0x1000>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301
302 interrupt-parent = <&intc>;
303 interrupts = <59>;
304
305 clocks = <&cgu X1830_CLK_SMB1>;
306
307 status = "disabled";
308 };
309
310 i2c2: i2c-controller@10052000 {
311 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
312 reg = <0x10052000 0x1000>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315
316 interrupt-parent = <&intc>;
317 interrupts = <58>;
318
319 clocks = <&cgu X1830_CLK_SMB2>;
320
321 status = "disabled";
322 };
323
324 dtrng: trng@10072000 {
325 compatible = "ingenic,x1830-dtrng";
326 reg = <0x10072000 0xc>;
327
328 clocks = <&cgu X1830_CLK_DTRNG>;
329
330 status = "disabled";
331 };
332
333 pdma: dma-controller@13420000 {
334 compatible = "ingenic,x1830-dma";
335 reg = <0x13420000 0x400>, <0x13421000 0x40>;
336
337 #dma-cells = <2>;
338
339 interrupt-parent = <&intc>;
340 interrupts = <10>;
341
342 clocks = <&cgu X1830_CLK_PDMA>;
343 };
344
345 msc0: mmc@13450000 {
346 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
347 reg = <0x13450000 0x1000>;
348
349 interrupt-parent = <&intc>;
350 interrupts = <37>;
351
352 clocks = <&cgu X1830_CLK_MSC0>;
353 clock-names = "mmc";
354
355 cap-sd-highspeed;
356 cap-mmc-highspeed;
357 cap-sdio-irq;
358
359 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
360 <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
361 dma-names = "rx", "tx";
362
363 status = "disabled";
364 };
365
366 msc1: mmc@13460000 {
367 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
368 reg = <0x13460000 0x1000>;
369
370 interrupt-parent = <&intc>;
371 interrupts = <36>;
372
373 clocks = <&cgu X1830_CLK_MSC1>;
374 clock-names = "mmc";
375
376 cap-sd-highspeed;
377 cap-mmc-highspeed;
378 cap-sdio-irq;
379
380 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
381 <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
382 dma-names = "rx", "tx";
383
384 status = "disabled";
385 };
386
387 mac: ethernet@134b0000 {
388 compatible = "ingenic,x1830-mac", "snps,dwmac";
389 reg = <0x134b0000 0x2000>;
390
391 interrupt-parent = <&intc>;
392 interrupts = <55>;
393 interrupt-names = "macirq";
394
395 clocks = <&cgu X1830_CLK_MAC>;
396 clock-names = "stmmaceth";
397
398 mode-reg = <&mac_phy_ctrl>;
399
400 status = "disabled";
401
402 mdio: mdio {
403 compatible = "snps,dwmac-mdio";
404 #address-cells = <1>;
405 #size-cells = <0>;
406
407 status = "disabled";
408 };
409 };
410
411 otg: usb@13500000 {
412 compatible = "ingenic,x1830-otg";
413 reg = <0x13500000 0x40000>;
414
415 interrupt-parent = <&intc>;
416 interrupts = <21>;
417
418 clocks = <&cgu X1830_CLK_OTG>;
419 clock-names = "otg";
420
421 phys = <&otg_phy>;
422 phy-names = "usb2-phy";
423
424 g-rx-fifo-size = <768>;
425 g-np-tx-fifo-size = <256>;
426 g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
427
428 status = "disabled";
429 };
430};