| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | /* |
| 3 | * Device Tree Source for the RZ/G2LC SMARC EVK board |
| 4 | * |
| 5 | * Copyright (C) 2021 Renesas Electronics Corp. |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | /* |
| 11 | * DIP-Switch SW1 setting on SoM |
| 12 | * 1 : High; 0: Low |
| 13 | * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) |
| 14 | * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) |
| 15 | * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) |
| 16 | * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) |
| 17 | * Please change below macros according to SW1 setting |
| 18 | */ |
| 19 | |
| 20 | #define SW_SD0_DEV_SEL 1 |
| 21 | |
| 22 | #define SW_SCIF_CAN 0 |
| 23 | #if (SW_SCIF_CAN) |
| 24 | /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ |
| 25 | #define SW_RSPI_CAN 0 |
| 26 | #else |
| 27 | /* Please set SW_RSPI_CAN. Default value is 1 */ |
| 28 | #define SW_RSPI_CAN 1 |
| 29 | #endif |
| 30 | |
| 31 | #if (SW_SCIF_CAN && SW_RSPI_CAN) |
| 32 | #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" |
| 33 | #endif |
| 34 | |
| 35 | /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ |
| 36 | #define PMOD1_SER0 1 |
| 37 | |
| 38 | /* |
| 39 | * To enable MTU3a PWM on PMOD0, |
| 40 | * - Set DIP-Switch SW1-4 to Off position. |
| 41 | * - Set SW_RSPI_CAN macro to 0. |
| 42 | * - Set PMOD_MTU3 macro to 1. |
| 43 | */ |
| 44 | #define PMOD_MTU3 0 |
| 45 | |
| 46 | #if (PMOD_MTU3 && SW_RSPI_CAN) |
| 47 | #error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" |
| 48 | #endif |
| 49 | |
| 50 | #include "r9a07g044c2.dtsi" |
| 51 | #include "rzg2lc-smarc-som.dtsi" |
| 52 | #include "rzg2lc-smarc.dtsi" |
| 53 | |
| 54 | / { |
| 55 | model = "Renesas SMARC EVK based on r9a07g044c2"; |
| 56 | compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; |
| 57 | }; |