| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Google Herobrine dts fragment for LTE SKUs |
| 4 | * |
| 5 | * Copyright 2022 Google LLC. |
| 6 | */ |
| 7 | /* Modem setup is different on Chrome setups than typical Qualcomm setup */ |
| 8 | |
| 9 | / { |
| 10 | reserved-memory { |
| 11 | mpss_mem: memory@8b800000 { |
| 12 | reg = <0x0 0x8b800000 0x0 0xf600000>; |
| 13 | no-map; |
| 14 | }; |
| 15 | |
| 16 | mba_mem: memory@9c700000 { |
| 17 | reg = <0x0 0x9c700000 0x0 0x200000>; |
| 18 | no-map; |
| 19 | }; |
| 20 | |
| 21 | mdata_mem: mpss-metadata { |
| 22 | alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; |
| 23 | size = <0x0 0x4000>; |
| 24 | no-map; |
| 25 | }; |
| 26 | }; |
| 27 | }; |
| 28 | |
| 29 | &ipa { |
| 30 | qcom,gsi-loader = "modem"; |
| 31 | status = "okay"; |
| 32 | }; |
| 33 | |
| 34 | &remoteproc_mpss { |
| 35 | compatible = "qcom,sc7280-mss-pil"; |
| 36 | |
| 37 | clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, |
| 38 | <&gcc GCC_MSS_OFFLINE_AXI_CLK>, |
| 39 | <&gcc GCC_MSS_SNOC_AXI_CLK>, |
| 40 | <&rpmhcc RPMH_PKA_CLK>, |
| 41 | <&rpmhcc RPMH_CXO_CLK>; |
| 42 | clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; |
| 43 | |
| 44 | iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; |
| 45 | interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; |
| 46 | memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; |
| 47 | firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", |
| 48 | "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; |
| 49 | |
| 50 | resets = <&aoss_reset AOSS_CC_MSS_RESTART>, |
| 51 | <&pdc_reset PDC_MODEM_SYNC_RESET>; |
| 52 | reset-names = "mss_restart", "pdc_reset"; |
| 53 | |
| 54 | qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; |
| 55 | qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; |
| 56 | qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; |
| 57 | |
| 58 | status = "okay"; |
| 59 | }; |
| 60 | |
| 61 | /* Increase the size from 2.5MB to 8MB */ |
| 62 | &rmtfs_mem { |
| 63 | reg = <0x0 0x9c900000 0x0 0x800000>; |
| 64 | }; |