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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / lg / lg1313.dtsi
blob: 3869460aa5dcb5da3a3fb32f8e0df6903b88862c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for lg1313 SoC
4 *
5 * Copyright (C) 2016, LG Electronics
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 compatible = "lge,lg1313";
16 interrupt-parent = <&gic>;
17
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a53";
25 reg = <0x0 0x0>;
26 next-level-cache = <&L2_0>;
27 };
28 cpu1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a53";
31 reg = <0x0 0x1>;
32 enable-method = "psci";
33 next-level-cache = <&L2_0>;
34 };
35 cpu2: cpu@2 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
38 reg = <0x0 0x2>;
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
41 };
42 cpu3: cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53";
45 reg = <0x0 0x3>;
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
48 };
49 L2_0: l2-cache0 {
50 compatible = "cache";
51 cache-level = <2>;
52 cache-unified;
53 };
54 };
55
56 psci {
57 compatible = "arm,psci-0.2", "arm,psci";
58 method = "smc";
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
62 };
63
64 gic: interrupt-controller@c0001000 {
65 #interrupt-cells = <3>;
66 compatible = "arm,gic-400";
67 interrupt-controller;
68 reg = <0x0 0xc0001000 0x1000>,
69 <0x0 0xc0002000 0x2000>,
70 <0x0 0xc0004000 0x2000>,
71 <0x0 0xc0006000 0x2000>;
72 };
73
74 pmu {
75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&cpu0>,
81 <&cpu1>,
82 <&cpu2>,
83 <&cpu3>;
84 };
85
86 timer {
87 compatible = "arm,armv8-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
89 IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
91 IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
93 IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
95 IRQ_TYPE_LEVEL_LOW)>;
96 };
97
98 clk_bus: clk_bus {
99 #clock-cells = <0>;
100
101 compatible = "fixed-clock";
102 clock-frequency = <198000000>;
103 clock-output-names = "BUSCLK";
104 };
105
106 soc {
107 #address-cells = <2>;
108 #size-cells = <1>;
109
110 compatible = "simple-bus";
111 interrupt-parent = <&gic>;
112 ranges;
113
114 eth0: ethernet@c3700000 {
115 compatible = "cdns,gem";
116 reg = <0x0 0xc3700000 0x1000>;
117 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&clk_bus>, <&clk_bus>;
119 clock-names = "hclk", "pclk";
120 phy-mode = "rmii";
121 /* Filled in by boot */
122 mac-address = [ 00 00 00 00 00 00 ];
123 };
124 };
125
126 amba {
127 #address-cells = <2>;
128 #size-cells = <1>;
129 #interrupt-cells = <3>;
130
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
133 ranges;
134
135 timers: timer@fd100000 {
136 compatible = "arm,sp804", "arm,primecell";
137 reg = <0x0 0xfd100000 0x1000>;
138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
140 clock-names = "timer0clk", "timer1clk", "apb_pclk";
141 };
142 wdog: watchdog@fd200000 {
143 compatible = "arm,sp805", "arm,primecell";
144 reg = <0x0 0xfd200000 0x1000>;
145 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clk_bus>, <&clk_bus>;
147 clock-names = "wdog_clk", "apb_pclk";
148 };
149 uart0: serial@fe000000 {
150 compatible = "arm,pl011", "arm,primecell";
151 reg = <0x0 0xfe000000 0x1000>;
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clk_bus>;
154 clock-names = "apb_pclk";
155 status = "disabled";
156 };
157 uart1: serial@fe100000 {
158 compatible = "arm,pl011", "arm,primecell";
159 reg = <0x0 0xfe100000 0x1000>;
160 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&clk_bus>;
162 clock-names = "apb_pclk";
163 status = "disabled";
164 };
165 uart2: serial@fe200000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x0 0xfe200000 0x1000>;
168 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&clk_bus>;
170 clock-names = "apb_pclk";
171 status = "disabled";
172 };
173 spi0: spi@fe800000 {
174 compatible = "arm,pl022", "arm,primecell";
175 reg = <0x0 0xfe800000 0x1000>;
176 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clk_bus>;
178 clock-names = "apb_pclk";
179 };
180 spi1: spi@fe900000 {
181 compatible = "arm,pl022", "arm,primecell";
182 reg = <0x0 0xfe900000 0x1000>;
183 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clk_bus>;
185 clock-names = "apb_pclk";
186 };
187 dmac0: dma-controller@c1128000 {
188 compatible = "arm,pl330", "arm,primecell";
189 reg = <0x0 0xc1128000 0x1000>;
190 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clk_bus>;
192 clock-names = "apb_pclk";
193 #dma-cells = <1>;
194 };
195 gpio0: gpio@fd400000 {
196 #gpio-cells = <2>;
197 compatible = "arm,pl061", "arm,primecell";
198 gpio-controller;
199 reg = <0x0 0xfd400000 0x1000>;
200 clocks = <&clk_bus>;
201 clock-names = "apb_pclk";
202 status = "disabled";
203 };
204 gpio1: gpio@fd410000 {
205 #gpio-cells = <2>;
206 compatible = "arm,pl061", "arm,primecell";
207 gpio-controller;
208 reg = <0x0 0xfd410000 0x1000>;
209 clocks = <&clk_bus>;
210 clock-names = "apb_pclk";
211 status = "disabled";
212 };
213 gpio2: gpio@fd420000 {
214 #gpio-cells = <2>;
215 compatible = "arm,pl061", "arm,primecell";
216 gpio-controller;
217 reg = <0x0 0xfd420000 0x1000>;
218 clocks = <&clk_bus>;
219 clock-names = "apb_pclk";
220 status = "disabled";
221 };
222 gpio3: gpio@fd430000 {
223 #gpio-cells = <2>;
224 compatible = "arm,pl061", "arm,primecell";
225 gpio-controller;
226 reg = <0x0 0xfd430000 0x1000>;
227 clocks = <&clk_bus>;
228 clock-names = "apb_pclk";
229 };
230 gpio4: gpio@fd440000 {
231 #gpio-cells = <2>;
232 compatible = "arm,pl061", "arm,primecell";
233 gpio-controller;
234 reg = <0x0 0xfd440000 0x1000>;
235 clocks = <&clk_bus>;
236 clock-names = "apb_pclk";
237 status = "disabled";
238 };
239 gpio5: gpio@fd450000 {
240 #gpio-cells = <2>;
241 compatible = "arm,pl061", "arm,primecell";
242 gpio-controller;
243 reg = <0x0 0xfd450000 0x1000>;
244 clocks = <&clk_bus>;
245 clock-names = "apb_pclk";
246 status = "disabled";
247 };
248 gpio6: gpio@fd460000 {
249 #gpio-cells = <2>;
250 compatible = "arm,pl061", "arm,primecell";
251 gpio-controller;
252 reg = <0x0 0xfd460000 0x1000>;
253 clocks = <&clk_bus>;
254 clock-names = "apb_pclk";
255 status = "disabled";
256 };
257 gpio7: gpio@fd470000 {
258 #gpio-cells = <2>;
259 compatible = "arm,pl061", "arm,primecell";
260 gpio-controller;
261 reg = <0x0 0xfd470000 0x1000>;
262 clocks = <&clk_bus>;
263 clock-names = "apb_pclk";
264 status = "disabled";
265 };
266 gpio8: gpio@fd480000 {
267 #gpio-cells = <2>;
268 compatible = "arm,pl061", "arm,primecell";
269 gpio-controller;
270 reg = <0x0 0xfd480000 0x1000>;
271 clocks = <&clk_bus>;
272 clock-names = "apb_pclk";
273 status = "disabled";
274 };
275 gpio9: gpio@fd490000 {
276 #gpio-cells = <2>;
277 compatible = "arm,pl061", "arm,primecell";
278 gpio-controller;
279 reg = <0x0 0xfd490000 0x1000>;
280 clocks = <&clk_bus>;
281 clock-names = "apb_pclk";
282 status = "disabled";
283 };
284 gpio10: gpio@fd4a0000 {
285 #gpio-cells = <2>;
286 compatible = "arm,pl061", "arm,primecell";
287 gpio-controller;
288 reg = <0x0 0xfd4a0000 0x1000>;
289 clocks = <&clk_bus>;
290 clock-names = "apb_pclk";
291 status = "disabled";
292 };
293 gpio11: gpio@fd4b0000 {
294 #gpio-cells = <2>;
295 compatible = "arm,pl061", "arm,primecell";
296 gpio-controller;
297 reg = <0x0 0xfd4b0000 0x1000>;
298 clocks = <&clk_bus>;
299 clock-names = "apb_pclk";
300 };
301 gpio12: gpio@fd4c0000 {
302 #gpio-cells = <2>;
303 compatible = "arm,pl061", "arm,primecell";
304 gpio-controller;
305 reg = <0x0 0xfd4c0000 0x1000>;
306 clocks = <&clk_bus>;
307 clock-names = "apb_pclk";
308 status = "disabled";
309 };
310 gpio13: gpio@fd4d0000 {
311 #gpio-cells = <2>;
312 compatible = "arm,pl061", "arm,primecell";
313 gpio-controller;
314 reg = <0x0 0xfd4d0000 0x1000>;
315 clocks = <&clk_bus>;
316 clock-names = "apb_pclk";
317 status = "disabled";
318 };
319 gpio14: gpio@fd4e0000 {
320 #gpio-cells = <2>;
321 compatible = "arm,pl061", "arm,primecell";
322 gpio-controller;
323 reg = <0x0 0xfd4e0000 0x1000>;
324 clocks = <&clk_bus>;
325 clock-names = "apb_pclk";
326 status = "disabled";
327 };
328 gpio15: gpio@fd4f0000 {
329 #gpio-cells = <2>;
330 compatible = "arm,pl061", "arm,primecell";
331 gpio-controller;
332 reg = <0x0 0xfd4f0000 0x1000>;
333 clocks = <&clk_bus>;
334 clock-names = "apb_pclk";
335 status = "disabled";
336 };
337 gpio16: gpio@fd500000 {
338 #gpio-cells = <2>;
339 compatible = "arm,pl061", "arm,primecell";
340 gpio-controller;
341 reg = <0x0 0xfd500000 0x1000>;
342 clocks = <&clk_bus>;
343 clock-names = "apb_pclk";
344 status = "disabled";
345 };
346 gpio17: gpio@fd510000 {
347 #gpio-cells = <2>;
348 compatible = "arm,pl061", "arm,primecell";
349 gpio-controller;
350 reg = <0x0 0xfd510000 0x1000>;
351 clocks = <&clk_bus>;
352 clock-names = "apb_pclk";
353 };
354 };
355};