| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | /* |
| 3 | * NXP S32G2 SoC family |
| 4 | * |
| 5 | * Copyright (c) 2021 SUSE LLC |
| 6 | * Copyright (c) 2017-2021 NXP |
| 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | |
| 11 | / { |
| 12 | compatible = "nxp,s32g2"; |
| 13 | interrupt-parent = <&gic>; |
| 14 | #address-cells = <2>; |
| 15 | #size-cells = <2>; |
| 16 | |
| 17 | cpus { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <0>; |
| 20 | |
| 21 | cpu0: cpu@0 { |
| 22 | device_type = "cpu"; |
| 23 | compatible = "arm,cortex-a53"; |
| 24 | reg = <0x0>; |
| 25 | enable-method = "psci"; |
| 26 | next-level-cache = <&cluster0_l2>; |
| 27 | }; |
| 28 | |
| 29 | cpu1: cpu@1 { |
| 30 | device_type = "cpu"; |
| 31 | compatible = "arm,cortex-a53"; |
| 32 | reg = <0x1>; |
| 33 | enable-method = "psci"; |
| 34 | next-level-cache = <&cluster0_l2>; |
| 35 | }; |
| 36 | |
| 37 | cpu2: cpu@100 { |
| 38 | device_type = "cpu"; |
| 39 | compatible = "arm,cortex-a53"; |
| 40 | reg = <0x100>; |
| 41 | enable-method = "psci"; |
| 42 | next-level-cache = <&cluster1_l2>; |
| 43 | }; |
| 44 | |
| 45 | cpu3: cpu@101 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,cortex-a53"; |
| 48 | reg = <0x101>; |
| 49 | enable-method = "psci"; |
| 50 | next-level-cache = <&cluster1_l2>; |
| 51 | }; |
| 52 | |
| 53 | cluster0_l2: l2-cache0 { |
| 54 | compatible = "cache"; |
| 55 | cache-level = <2>; |
| 56 | cache-unified; |
| 57 | }; |
| 58 | |
| 59 | cluster1_l2: l2-cache1 { |
| 60 | compatible = "cache"; |
| 61 | cache-level = <2>; |
| 62 | cache-unified; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | pmu { |
| 67 | compatible = "arm,cortex-a53-pmu"; |
| 68 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 69 | }; |
| 70 | |
| 71 | timer { |
| 72 | compatible = "arm,armv8-timer"; |
| 73 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 74 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 75 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 76 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 77 | }; |
| 78 | |
| 79 | firmware { |
| 80 | psci { |
| 81 | compatible = "arm,psci-1.0"; |
| 82 | method = "smc"; |
| 83 | }; |
| 84 | }; |
| 85 | |
| 86 | soc@0 { |
| 87 | compatible = "simple-bus"; |
| 88 | #address-cells = <1>; |
| 89 | #size-cells = <1>; |
| 90 | ranges = <0 0 0 0x80000000>; |
| 91 | |
| 92 | uart0: serial@401c8000 { |
| 93 | compatible = "nxp,s32g2-linflexuart", |
| 94 | "fsl,s32v234-linflexuart"; |
| 95 | reg = <0x401c8000 0x3000>; |
| 96 | interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; |
| 97 | status = "disabled"; |
| 98 | }; |
| 99 | |
| 100 | uart1: serial@401cc000 { |
| 101 | compatible = "nxp,s32g2-linflexuart", |
| 102 | "fsl,s32v234-linflexuart"; |
| 103 | reg = <0x401cc000 0x3000>; |
| 104 | interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; |
| 105 | status = "disabled"; |
| 106 | }; |
| 107 | |
| 108 | uart2: serial@402bc000 { |
| 109 | compatible = "nxp,s32g2-linflexuart", |
| 110 | "fsl,s32v234-linflexuart"; |
| 111 | reg = <0x402bc000 0x3000>; |
| 112 | interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; |
| 113 | status = "disabled"; |
| 114 | }; |
| 115 | |
| 116 | gic: interrupt-controller@50800000 { |
| 117 | compatible = "arm,gic-v3"; |
| 118 | reg = <0x50800000 0x10000>, |
| 119 | <0x50880000 0x80000>, |
| 120 | <0x50400000 0x2000>, |
| 121 | <0x50410000 0x2000>, |
| 122 | <0x50420000 0x2000>; |
| 123 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 124 | interrupt-controller; |
| 125 | #interrupt-cells = <3>; |
| 126 | }; |
| 127 | }; |
| 128 | }; |