Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Supports Symphony evaluation board versions >= 1.4a. |
| 4 | * |
| 5 | * Copyright 2019-2020 Variscite Ltd. |
| 6 | * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include <dt-bindings/usb/pd.h> |
| 12 | #include "imx8mn-var-som.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; |
| 16 | compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; |
| 17 | |
| 18 | reg_usdhc2_vmmc: regulator-usdhc2-vmmc { |
| 19 | compatible = "regulator-fixed"; |
| 20 | pinctrl-names = "default"; |
| 21 | pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| 22 | regulator-name = "VSD_3V3"; |
| 23 | regulator-min-microvolt = <3300000>; |
| 24 | regulator-max-microvolt = <3300000>; |
| 25 | gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; |
| 26 | enable-active-high; |
| 27 | }; |
| 28 | |
| 29 | gpio-keys { |
| 30 | compatible = "gpio-keys"; |
| 31 | |
| 32 | key-back { |
| 33 | label = "Back"; |
| 34 | gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; |
| 35 | linux,code = <KEY_BACK>; |
| 36 | }; |
| 37 | |
| 38 | key-home { |
| 39 | label = "Home"; |
| 40 | gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; |
| 41 | linux,code = <KEY_HOME>; |
| 42 | }; |
| 43 | |
| 44 | key-menu { |
| 45 | label = "Menu"; |
| 46 | gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; |
| 47 | linux,code = <KEY_MENU>; |
| 48 | }; |
| 49 | }; |
| 50 | |
| 51 | leds { |
| 52 | compatible = "gpio-leds"; |
| 53 | |
| 54 | led { |
| 55 | label = "Heartbeat"; |
| 56 | gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; |
| 57 | linux,default-trigger = "heartbeat"; |
| 58 | }; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | ðphy { |
| 63 | reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; |
| 64 | }; |
| 65 | |
| 66 | &i2c2 { |
| 67 | clock-frequency = <400000>; |
| 68 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&pinctrl_i2c2>; |
| 70 | status = "okay"; |
| 71 | |
| 72 | pca9534: gpio@20 { |
| 73 | compatible = "nxp,pca9534"; |
| 74 | reg = <0x20>; |
| 75 | gpio-controller; |
| 76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&pinctrl_pca9534>; |
| 78 | interrupt-parent = <&gpio1>; |
| 79 | interrupts = <7 IRQ_TYPE_EDGE_FALLING>; |
| 80 | #gpio-cells = <2>; |
| 81 | wakeup-source; |
| 82 | |
| 83 | /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ |
| 84 | usb3-sata-sel-hog { |
| 85 | gpio-hog; |
| 86 | gpios = <4 GPIO_ACTIVE_HIGH>; |
| 87 | output-low; |
| 88 | line-name = "usb3_sata_sel"; |
| 89 | }; |
| 90 | |
| 91 | som-vselect-hog { |
| 92 | gpio-hog; |
| 93 | gpios = <6 GPIO_ACTIVE_HIGH>; |
| 94 | output-low; |
| 95 | line-name = "som_vselect"; |
| 96 | }; |
| 97 | |
| 98 | enet-sel-hog { |
| 99 | gpio-hog; |
| 100 | gpios = <7 GPIO_ACTIVE_HIGH>; |
| 101 | output-low; |
| 102 | line-name = "enet_sel"; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | /* |
| 107 | * For Symphony board version <= 1.4, the PTN5150 IRQ pin is connected |
| 108 | * to GPIO1_IO11 on the SoM (R106 present, R132 absent). From Symphony |
| 109 | * board version >= 1.4a, the PTN5150 ID pin is connected to GPIO1_IO11 |
| 110 | * on the SoM (R106 absent, R132 present). |
| 111 | */ |
| 112 | extcon_usbotg1: typec@3d { |
| 113 | compatible = "nxp,ptn5150"; |
| 114 | reg = <0x3d>; |
| 115 | interrupt-parent = <&gpio1>; |
| 116 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pinctrl_ptn5150>; |
| 119 | status = "okay"; |
| 120 | |
| 121 | port { |
| 122 | typec1_dr_sw: endpoint { |
| 123 | remote-endpoint = <&usb1_drd_sw>; |
| 124 | }; |
| 125 | }; |
| 126 | }; |
| 127 | }; |
| 128 | |
| 129 | &i2c3 { |
| 130 | /* Capacitive touch controller */ |
| 131 | ft5x06_ts: touchscreen@38 { |
| 132 | compatible = "edt,edt-ft5406"; |
| 133 | reg = <0x38>; |
| 134 | pinctrl-names = "default"; |
| 135 | pinctrl-0 = <&pinctrl_captouch>; |
| 136 | interrupt-parent = <&gpio5>; |
| 137 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | |
| 139 | touchscreen-size-x = <800>; |
| 140 | touchscreen-size-y = <480>; |
| 141 | touchscreen-inverted-x; |
| 142 | touchscreen-inverted-y; |
| 143 | }; |
| 144 | |
| 145 | rtc@68 { |
| 146 | compatible = "dallas,ds1337"; |
| 147 | reg = <0x68>; |
| 148 | }; |
| 149 | }; |
| 150 | |
| 151 | /* Header */ |
| 152 | &uart1 { |
| 153 | pinctrl-names = "default"; |
| 154 | pinctrl-0 = <&pinctrl_uart1>; |
| 155 | status = "okay"; |
| 156 | }; |
| 157 | |
| 158 | /* Header */ |
| 159 | &uart3 { |
| 160 | pinctrl-names = "default"; |
| 161 | pinctrl-0 = <&pinctrl_uart3>; |
| 162 | status = "okay"; |
| 163 | }; |
| 164 | |
| 165 | &usbotg1 { |
| 166 | dr_mode = "otg"; |
| 167 | hnp-disable; |
| 168 | srp-disable; |
| 169 | adp-disable; |
| 170 | usb-role-switch; |
| 171 | disable-over-current; |
| 172 | samsung,picophy-pre-emp-curr-control = <3>; |
| 173 | samsung,picophy-dc-vol-level-adjust = <7>; |
| 174 | status = "okay"; |
| 175 | |
| 176 | port { |
| 177 | usb1_drd_sw: endpoint { |
| 178 | remote-endpoint = <&typec1_dr_sw>; |
| 179 | }; |
| 180 | }; |
| 181 | }; |
| 182 | |
| 183 | &iomuxc { |
| 184 | pinctrl_captouch: captouchgrp { |
| 185 | fsl,pins = < |
| 186 | MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 |
| 187 | >; |
| 188 | }; |
| 189 | |
| 190 | pinctrl_i2c2: i2c2grp { |
| 191 | fsl,pins = < |
| 192 | MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| 193 | MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| 194 | >; |
| 195 | }; |
| 196 | |
| 197 | pinctrl_pca9534: pca9534grp { |
| 198 | fsl,pins = < |
| 199 | MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 |
| 200 | >; |
| 201 | }; |
| 202 | |
| 203 | pinctrl_ptn5150: ptn5150grp { |
| 204 | fsl,pins = < |
| 205 | MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 |
| 206 | >; |
| 207 | }; |
| 208 | |
| 209 | pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { |
| 210 | fsl,pins = < |
| 211 | MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 |
| 212 | >; |
| 213 | }; |
| 214 | |
| 215 | pinctrl_uart1: uart1grp { |
| 216 | fsl,pins = < |
| 217 | MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 |
| 218 | MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 |
| 219 | >; |
| 220 | }; |
| 221 | |
| 222 | pinctrl_uart3: uart3grp { |
| 223 | fsl,pins = < |
| 224 | MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 |
| 225 | MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 |
| 226 | >; |
| 227 | }; |
| 228 | }; |