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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / ti / omap / omap3-beagle.dts
blob: 4d9a8eab6abf8030f2801a3c1cef8f7eda085dd6 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 */
5/dts-v1/;
6
7#include "omap34xx.dtsi"
8
9/ {
10 model = "TI OMAP3 BeagleBoard";
11 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&vcc>;
16 };
17 };
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x80000000 0x10000000>; /* 256 MB */
22 };
23
24 aliases {
25 display0 = &dvi0;
26 display1 = &tv0;
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 led-pmu-stat {
32 label = "beagleboard::pmu_stat";
33 gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
34 };
35
36 led-heartbeat {
37 label = "beagleboard::usr0";
38 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
39 linux,default-trigger = "heartbeat";
40 };
41
42 led-mmc {
43 label = "beagleboard::usr1";
44 gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
45 linux,default-trigger = "mmc0";
46 };
47 };
48
49 /* HS USB Port 2 Power */
50 hsusb2_power: hsusb2_power_reg {
51 compatible = "regulator-fixed";
52 regulator-name = "hsusb2_vbus";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */
56 startup-delay-us = <70000>;
57 };
58
59 /* HS USB Host PHY on PORT 2 */
60 hsusb2_phy: hsusb2-phy-pins {
61 compatible = "usb-nop-xceiv";
62 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
63 vcc-supply = <&hsusb2_power>;
64 #phy-cells = <0>;
65 };
66
67 sound {
68 compatible = "ti,omap-twl4030";
69 ti,model = "omap3beagle";
70
71 ti,mcbsp = <&mcbsp2>;
72 };
73
74 gpio_keys {
75 compatible = "gpio-keys";
76
77 user {
78 label = "user";
79 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
80 linux,code = <0x114>;
81 wakeup-source;
82 };
83
84 };
85
86 tfp410: encoder0 {
87 compatible = "ti,tfp410";
88 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
89
90 pinctrl-names = "default";
91 pinctrl-0 = <&tfp410_pins>;
92
93 ports {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 port@0 {
98 reg = <0>;
99
100 tfp410_in: endpoint {
101 remote-endpoint = <&dpi_out>;
102 };
103 };
104
105 port@1 {
106 reg = <1>;
107
108 tfp410_out: endpoint {
109 remote-endpoint = <&dvi_connector_in>;
110 };
111 };
112 };
113 };
114
115 dvi0: connector0 {
116 compatible = "dvi-connector";
117 label = "dvi";
118
119 digital;
120
121 ddc-i2c-bus = <&i2c3>;
122
123 port {
124 dvi_connector_in: endpoint {
125 remote-endpoint = <&tfp410_out>;
126 };
127 };
128 };
129
130 tv0: connector1 {
131 compatible = "svideo-connector";
132 label = "tv";
133
134 port {
135 tv_connector_in: endpoint {
136 remote-endpoint = <&venc_out>;
137 };
138 };
139 };
140
141 etb@540000000 {
142 compatible = "arm,coresight-etb10", "arm,primecell";
143 reg = <0x5401b000 0x1000>;
144
145 clocks = <&emu_src_ck>;
146 clock-names = "apb_pclk";
147 in-ports {
148 port {
149 etb_in: endpoint {
150 remote-endpoint = <&etm_out>;
151 };
152 };
153 };
154 };
155
156 etm@54010000 {
157 compatible = "arm,coresight-etm3x", "arm,primecell";
158 reg = <0x54010000 0x1000>;
159
160 clocks = <&emu_src_ck>;
161 clock-names = "apb_pclk";
162 out-ports {
163 port {
164 etm_out: endpoint {
165 remote-endpoint = <&etb_in>;
166 };
167 };
168 };
169 };
170};
171
172&omap3_pmx_wkup {
173 gpio1_pins: gpio1-pins {
174 pinctrl-single,pins = <
175 OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
176 >;
177 };
178};
179
180&omap3_pmx_core {
181 pinctrl-names = "default";
182 pinctrl-0 = <
183 &hsusb2_pins
184 >;
185
186 hsusb2_pins: hsusb2-pins {
187 pinctrl-single,pins = <
188 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
189 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
190 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
191 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
192 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
193 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
194 >;
195 };
196
197 uart3_pins: uart3-pins {
198 pinctrl-single,pins = <
199 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
200 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
201 >;
202 };
203
204 tfp410_pins: tfp410-pins {
205 pinctrl-single,pins = <
206 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
207 >;
208 };
209
210 dss_dpi_pins: dss-dpi-pins {
211 pinctrl-single,pins = <
212 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
213 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
214 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
215 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
216 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
217 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
218 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
219 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
220 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
221 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
222 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
223 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
224 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
225 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
226 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
227 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
228 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
229 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
230 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
231 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
232 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
233 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
234 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
235 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
236 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
237 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
238 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
239 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
240 >;
241 };
242};
243
244&omap3_pmx_core2 {
245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &hsusb2_2_pins
248 >;
249
250 hsusb2_2_pins: hsusb2-2-pins {
251 pinctrl-single,pins = <
252 OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
253 OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
254 OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
255 OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
256 OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
257 OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
258 >;
259 };
260};
261
262&i2c1 {
263 clock-frequency = <2600000>;
264
265 twl: twl@48 {
266 reg = <0x48>;
267 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
268 interrupt-parent = <&intc>;
269
270 twl_audio: audio {
271 compatible = "ti,twl4030-audio";
272 codec {
273 };
274 };
275 };
276};
277
278#include "twl4030.dtsi"
279#include "twl4030_omap3.dtsi"
280
281&i2c3 {
282 clock-frequency = <100000>;
283};
284
285&mmc1 {
286 vmmc-supply = <&vmmc1>;
287 vqmmc-supply = <&vsim>;
288 bus-width = <8>;
289};
290
291&mmc2 {
292 status = "disabled";
293};
294
295&mmc3 {
296 status = "disabled";
297};
298
299&usbhshost {
300 port2-mode = "ehci-phy";
301};
302
303&usbhsehci {
304 phys = <0 &hsusb2_phy>;
305};
306
307&twl_gpio {
308 ti,use-leds;
309 /* pullups: BIT(1) */
310 ti,pullups = <0x000002>;
311 /*
312 * pulldowns:
313 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
314 * BIT(15), BIT(16), BIT(17)
315 */
316 ti,pulldowns = <0x03a1c4>;
317};
318
319&uart3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart3_pins>;
322 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
323};
324
325&gpio1 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&gpio1_pins>;
328};
329
330&usb_otg_hs {
331 interface-type = <0>;
332 usb-phy = <&usb2_phy>;
333 phys = <&usb2_phy>;
334 phy-names = "usb2-phy";
335 mode = <3>;
336 power = <50>;
337};
338
339&vaux2 {
340 regulator-name = "vdd_ehci";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-always-on;
344};
345
346&mcbsp2 {
347 status = "okay";
348};
349
350/* Needed to power the DPI pins */
351&vpll2 {
352 regulator-always-on;
353};
354
355&dss {
356 status = "okay";
357
358 pinctrl-names = "default";
359 pinctrl-0 = <&dss_dpi_pins>;
360
361 port {
362 dpi_out: endpoint {
363 remote-endpoint = <&tfp410_in>;
364 data-lines = <24>;
365 };
366 };
367};
368
369&venc {
370 status = "okay";
371
372 vdda-supply = <&vdac>;
373
374 port {
375 venc_out: endpoint {
376 remote-endpoint = <&tv_connector_in>;
377 ti,channels = <2>;
378 };
379 };
380};
381
382&gpmc {
383 status = "okay";
384 ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
385
386 /* Chip select 0 */
387 nand@0,0 {
388 compatible = "ti,omap2-nand";
389 reg = <0 0 4>; /* NAND I/O window, 4 bytes */
390 interrupt-parent = <&gpmc>;
391 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
392 <1 IRQ_TYPE_NONE>; /* termcount */
393 ti,nand-ecc-opt = "ham1";
394 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
395 nand-bus-width = <16>;
396 #address-cells = <1>;
397 #size-cells = <1>;
398
399 gpmc,device-width = <2>;
400 gpmc,cs-on-ns = <0>;
401 gpmc,cs-rd-off-ns = <36>;
402 gpmc,cs-wr-off-ns = <36>;
403 gpmc,adv-on-ns = <6>;
404 gpmc,adv-rd-off-ns = <24>;
405 gpmc,adv-wr-off-ns = <36>;
406 gpmc,oe-on-ns = <6>;
407 gpmc,oe-off-ns = <48>;
408 gpmc,we-on-ns = <6>;
409 gpmc,we-off-ns = <30>;
410 gpmc,rd-cycle-ns = <72>;
411 gpmc,wr-cycle-ns = <72>;
412 gpmc,access-ns = <54>;
413 gpmc,wr-access-ns = <30>;
414
415 partition@0 {
416 label = "X-Loader";
417 reg = <0 0x80000>;
418 };
419 partition@80000 {
420 label = "U-Boot";
421 reg = <0x80000 0x1e0000>;
422 };
423 partition@1c0000 {
424 label = "U-Boot Env";
425 reg = <0x260000 0x20000>;
426 };
427 partition@280000 {
428 label = "Kernel";
429 reg = <0x280000 0x400000>;
430 };
431 partition@780000 {
432 label = "Filesystem";
433 reg = <0x680000 0xf980000>;
434 };
435 };
436};