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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / ti / keystone / keystone-k2l.dtsi
blob: 2062fe561642fbe26157b9ee12838702a49d0a09 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Keystone 2 Lamarr SoC specific device tree
4 *
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/reset/ti-syscon.h>
9
10/ {
11 compatible = "ti,k2l", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Lamarr SoC";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 interrupt-parent = <&gic>;
19
20 cpu@0 {
21 compatible = "arm,cortex-a15";
22 device_type = "cpu";
23 reg = <0>;
24 };
25
26 cpu@1 {
27 compatible = "arm,cortex-a15";
28 device_type = "cpu";
29 reg = <1>;
30 };
31 };
32
33 aliases {
34 rproc0 = &dsp0;
35 rproc1 = &dsp1;
36 rproc2 = &dsp2;
37 rproc3 = &dsp3;
38 };
39};
40
41&soc0 {
42 /include/ "keystone-k2l-clocks.dtsi"
43
44 uart2: serial@2348400 {
45 compatible = "ti,da830-uart", "ns16550a";
46 current-speed = <115200>;
47 reg-shift = <2>;
48 reg-io-width = <4>;
49 reg = <0x02348400 0x100>;
50 clocks = <&clkuart2>;
51 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
52 };
53
54 uart3: serial@2348800 {
55 compatible = "ti,da830-uart", "ns16550a";
56 current-speed = <115200>;
57 reg-shift = <2>;
58 reg-io-width = <4>;
59 reg = <0x02348800 0x100>;
60 clocks = <&clkuart3>;
61 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
62 };
63
64 gpio1: gpio@2348000 {
65 compatible = "ti,keystone-gpio";
66 reg = <0x02348000 0x100>;
67 gpio-controller;
68 #gpio-cells = <2>;
69 /* HW Interrupts mapped to GPIO pins */
70 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
71 <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
72 <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
73 <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
74 <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
75 <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
76 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
77 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
78 <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
79 <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
80 <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
81 <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
82 <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
83 <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
84 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
85 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
86 <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
87 <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
88 <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
89 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
90 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
91 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
92 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
93 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
94 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
95 <GIC_SPI 401 IRQ_TYPE_EDGE_RISING>,
96 <GIC_SPI 402 IRQ_TYPE_EDGE_RISING>,
97 <GIC_SPI 403 IRQ_TYPE_EDGE_RISING>,
98 <GIC_SPI 404 IRQ_TYPE_EDGE_RISING>,
99 <GIC_SPI 405 IRQ_TYPE_EDGE_RISING>,
100 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
101 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>;
102 clocks = <&clkgpio>;
103 clock-names = "gpio";
104 ti,ngpio = <32>;
105 ti,davinci-gpio-unbanked = <32>;
106 };
107
108 k2l_pmx: pinmux@2620690 {
109 compatible = "pinctrl-single";
110 reg = <0x02620690 0xc>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 #pinctrl-cells = <2>;
114 pinctrl-single,bit-per-mux;
115 pinctrl-single,register-width = <32>;
116 pinctrl-single,function-mask = <0x1>;
117 status = "disabled";
118
119 uart3_emifa_pins: uart3-emifa-pins {
120 pinctrl-single,bits = <
121 /* UART3_EMIFA_SEL */
122 0x0 0x0 0xc0
123 >;
124 };
125
126 uart2_emifa_pins: uart2-emifa-pins {
127 pinctrl-single,bits = <
128 /* UART2_EMIFA_SEL */
129 0x0 0x0 0x30
130 >;
131 };
132
133 uart01_spi2_pins: uart01-spi2-pins {
134 pinctrl-single,bits = <
135 /* UART01_SPI2_SEL */
136 0x0 0x0 0x4
137 >;
138 };
139
140 dfesync_rp1_pins: dfesync-rp1-pins {
141 pinctrl-single,bits = <
142 /* DFESYNC_RP1_SEL */
143 0x0 0x0 0x2
144 >;
145 };
146
147 avsif_pins: avsif-pins {
148 pinctrl-single,bits = <
149 /* AVSIF_SEL */
150 0x0 0x0 0x1
151 >;
152 };
153
154 gpio_emu_pins: gpio-emu-pins {
155 pinctrl-single,bits = <
156 /*
157 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
158 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
159 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
160 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
161 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
162 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
163 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
164 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
165 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
166 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
167 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
168 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
169 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
170 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
171 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
172 */
173 0x4 0x0000 0xfffe0000
174 >;
175 };
176
177 gpio_timio_pins: gpio-timio-pins {
178 pinctrl-single,bits = <
179 /*
180 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
181 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
182 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
183 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
184 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
185 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
186 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
187 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
188 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
189 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
190 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
191 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
192 */
193 0x4 0x0 0xfff0
194 >;
195 };
196
197 gpio_spi2cs_pins: gpio-spi2cs-pins {
198 pinctrl-single,bits = <
199 /*
200 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
201 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
202 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
203 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
204 */
205 0x4 0x0 0xf
206 >;
207 };
208
209 gpio_dfeio_pins: gpio-dfeio-pins {
210 pinctrl-single,bits = <
211 /*
212 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
213 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
214 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
215 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
216 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
217 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
218 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
219 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
220 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
221 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
222 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
223 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
224 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
225 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
226 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
227 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
228 */
229 0x8 0x0 0xffff0000
230 >;
231 };
232
233 gpio_emifa_pins: gpio-emifa-pins {
234 pinctrl-single,bits = <
235 /*
236 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
237 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
238 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
239 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
240 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
241 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
242 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
243 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
244 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
245 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
246 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
247 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
248 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
249 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
250 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
251 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
252 */
253 0x8 0x0 0xffff
254 >;
255 };
256 };
257
258 msm_ram: sram@c000000 {
259 compatible = "mmio-sram";
260 reg = <0x0c000000 0x200000>;
261 ranges = <0x0 0x0c000000 0x200000>;
262 #address-cells = <1>;
263 #size-cells = <1>;
264
265 bm-sram@1f8000 {
266 reg = <0x001f8000 0x8000>;
267 };
268 };
269
270 psc: power-sleep-controller@2350000 {
271 pscrst: reset-controller {
272 compatible = "ti,k2l-pscrst", "ti,syscon-reset";
273 #reset-cells = <1>;
274
275 ti,reset-bits = <
276 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
277 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
278 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
279 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
280 >;
281 };
282 };
283
284 osr: sram@70000000 {
285 compatible = "mmio-sram";
286 reg = <0x70000000 0x10000>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 clocks = <&clkosr>;
290 };
291
292 devctrl: device-state-control@2620000 {
293 dspgpio0: keystone_dsp_gpio@240 {
294 compatible = "ti,keystone-dsp-gpio";
295 reg = <0x240 0x4>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 gpio,syscon-dev = <&devctrl 0x240>;
299 };
300
301 dspgpio1: keystone_dsp_gpio@244 {
302 compatible = "ti,keystone-dsp-gpio";
303 reg = <0x244 0x4>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 gpio,syscon-dev = <&devctrl 0x244>;
307 };
308
309 dspgpio2: keystone_dsp_gpio@248 {
310 compatible = "ti,keystone-dsp-gpio";
311 reg = <0x248 0x4>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 gpio,syscon-dev = <&devctrl 0x248>;
315 };
316
317 dspgpio3: keystone_dsp_gpio@24c {
318 compatible = "ti,keystone-dsp-gpio";
319 reg = <0x24c 0x4>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 gpio,syscon-dev = <&devctrl 0x24c>;
323 };
324 };
325
326 dsp0: dsp@10800000 {
327 compatible = "ti,k2l-dsp";
328 reg = <0x10800000 0x00100000>,
329 <0x10e00000 0x00008000>,
330 <0x10f00000 0x00008000>;
331 reg-names = "l2sram", "l1pram", "l1dram";
332 clocks = <&clkgem0>;
333 ti,syscon-dev = <&devctrl 0x844>;
334 resets = <&pscrst 0>;
335 interrupt-parent = <&kirq0>;
336 interrupts = <0 8>;
337 interrupt-names = "vring", "exception";
338 kick-gpios = <&dspgpio0 27 0>;
339 status = "disabled";
340 };
341
342 dsp1: dsp@11800000 {
343 compatible = "ti,k2l-dsp";
344 reg = <0x11800000 0x00100000>,
345 <0x11e00000 0x00008000>,
346 <0x11f00000 0x00008000>;
347 reg-names = "l2sram", "l1pram", "l1dram";
348 clocks = <&clkgem1>;
349 ti,syscon-dev = <&devctrl 0x848>;
350 resets = <&pscrst 1>;
351 interrupt-parent = <&kirq0>;
352 interrupts = <1 9>;
353 interrupt-names = "vring", "exception";
354 kick-gpios = <&dspgpio1 27 0>;
355 status = "disabled";
356 };
357
358 dsp2: dsp@12800000 {
359 compatible = "ti,k2l-dsp";
360 reg = <0x12800000 0x00100000>,
361 <0x12e00000 0x00008000>,
362 <0x12f00000 0x00008000>;
363 reg-names = "l2sram", "l1pram", "l1dram";
364 clocks = <&clkgem2>;
365 ti,syscon-dev = <&devctrl 0x84c>;
366 resets = <&pscrst 2>;
367 interrupt-parent = <&kirq0>;
368 interrupts = <2 10>;
369 interrupt-names = "vring", "exception";
370 kick-gpios = <&dspgpio2 27 0>;
371 status = "disabled";
372 };
373
374 dsp3: dsp@13800000 {
375 compatible = "ti,k2l-dsp";
376 reg = <0x13800000 0x00100000>,
377 <0x13e00000 0x00008000>,
378 <0x13f00000 0x00008000>;
379 reg-names = "l2sram", "l1pram", "l1dram";
380 clocks = <&clkgem3>;
381 ti,syscon-dev = <&devctrl 0x850>;
382 resets = <&pscrst 3>;
383 interrupt-parent = <&kirq0>;
384 interrupts = <3 11>;
385 interrupt-names = "vring", "exception";
386 kick-gpios = <&dspgpio3 27 0>;
387 status = "disabled";
388 };
389
390 mdio: mdio@26200f00 {
391 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0x26200f00 0x100>;
395 status = "disabled";
396 clocks = <&clkcpgmac>;
397 clock-names = "fck";
398 bus_freq = <2500000>;
399 };
400 /include/ "keystone-k2l-netcp.dtsi"
401};
402
403&spi0 {
404 ti,davinci-spi-num-cs = <5>;
405};
406
407&spi1 {
408 ti,davinci-spi-num-cs = <3>;
409};
410
411&spi2 {
412 ti,davinci-spi-num-cs = <5>;
413 /* Pin muxed. Enabled and configured by Bootloader */
414 status = "disabled";
415};