blob: df451c3c2a26d77ec141e1cfb68d12b38886dd36 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include "stm32mp131.dtsi"
8
9/ {
10 soc {
11 m_can1: can@4400e000 {
12 compatible = "bosch,m_can";
13 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
14 reg-names = "m_can", "message_ram";
15 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
16 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
17 interrupt-names = "int0", "int1";
18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
21 status = "disabled";
22 };
23
24 m_can2: can@4400f000 {
25 compatible = "bosch,m_can";
26 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
27 reg-names = "m_can", "message_ram";
28 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
30 interrupt-names = "int0", "int1";
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
34 status = "disabled";
35 };
36
37 adc_1: adc@48003000 {
38 compatible = "st,stm32mp13-adc-core";
39 reg = <0x48003000 0x400>;
40 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
42 clock-names = "bus", "adc";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
47 status = "disabled";
48
49 adc1: adc@0 {
50 compatible = "st,stm32mp13-adc";
51 #io-channel-cells = <1>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <0x0>;
55 interrupt-parent = <&adc_1>;
56 interrupts = <0>;
57 dmas = <&dmamux1 9 0x400 0x80000001>;
58 dma-names = "rx";
59 status = "disabled";
60
61 channel@18 {
62 reg = <18>;
63 label = "vrefint";
64 };
65 };
66 };
67 };
68};