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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / qcom / qcom-msm8660.dtsi
blob: 78023ed2fdf71f5168692d43a8b9d80573666545 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "qcom,scorpion";
22 enable-method = "qcom,gcc-msm8660";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 };
27
28 cpu@1 {
29 compatible = "qcom,scorpion";
30 enable-method = "qcom,gcc-msm8660";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x0 0x0>;
46 };
47
48 cpu-pmu {
49 compatible = "qcom,scorpion-mp-pmu";
50 interrupts = <1 9 0x304>;
51 };
52
53 clocks {
54 cxo_board: cxo-board-clk {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
59 };
60
61 pxo_board: pxo-board-clk {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
66 };
67
68 sleep-clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
73 };
74 };
75
76 /*
77 * These channels from the ADC are simply hardware monitors.
78 * That is why the ADC is referred to as "HKADC" - HouseKeeping
79 * ADC.
80 */
81 iio-hwmon {
82 compatible = "iio-hwmon";
83 io-channels = <&xoadc 0x00 0x01>, /* Battery */
84 <&xoadc 0x00 0x02>, /* DC in (charger) */
85 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
86 <&xoadc 0x00 0x0b>, /* Die temperature */
87 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
88 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
89 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
90 };
91
92 soc: soc {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 compatible = "simple-bus";
97
98 intc: interrupt-controller@2080000 {
99 compatible = "qcom,msm-8660-qgic";
100 interrupt-controller;
101 #interrupt-cells = <3>;
102 reg = < 0x02080000 0x1000 >,
103 < 0x02081000 0x1000 >;
104 };
105
106 timer@2000000 {
107 compatible = "qcom,scss-timer", "qcom,msm-timer";
108 interrupts = <1 0 0x301>,
109 <1 1 0x301>,
110 <1 2 0x301>;
111 reg = <0x02000000 0x100>;
112 clock-frequency = <27000000>,
113 <32768>;
114 cpu-offset = <0x40000>;
115 };
116
117 tlmm: pinctrl@800000 {
118 compatible = "qcom,msm8660-pinctrl";
119 reg = <0x800000 0x4000>;
120
121 gpio-controller;
122 gpio-ranges = <&tlmm 0 0 173>;
123 #gpio-cells = <2>;
124 interrupts = <0 16 0x4>;
125 interrupt-controller;
126 #interrupt-cells = <2>;
127
128 };
129
130 gcc: clock-controller@900000 {
131 compatible = "qcom,gcc-msm8660";
132 #clock-cells = <1>;
133 #power-domain-cells = <1>;
134 #reset-cells = <1>;
135 reg = <0x900000 0x4000>;
136 clocks = <&pxo_board>, <&cxo_board>;
137 clock-names = "pxo", "cxo";
138 };
139
140 gsbi1: gsbi@16000000 {
141 compatible = "qcom,gsbi-v1.0.0";
142 cell-index = <12>;
143 reg = <0x16000000 0x100>;
144 clocks = <&gcc GSBI1_H_CLK>;
145 clock-names = "iface";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges;
149
150 syscon-tcsr = <&tcsr>;
151
152 status = "disabled";
153
154 gsbi1_spi: spi@16080000 {
155 compatible = "qcom,spi-qup-v1.1.1";
156 reg = <0x16080000 0x1000>;
157 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
159 clock-names = "core", "iface";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 status = "disabled";
163 };
164 };
165
166 gsbi3: gsbi@16200000 {
167 compatible = "qcom,gsbi-v1.0.0";
168 cell-index = <12>;
169 reg = <0x16200000 0x100>;
170 clocks = <&gcc GSBI3_H_CLK>;
171 clock-names = "iface";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 syscon-tcsr = <&tcsr>;
177 status = "disabled";
178
179 gsbi3_i2c: i2c@16280000 {
180 compatible = "qcom,i2c-qup-v1.1.1";
181 reg = <0x16280000 0x1000>;
182 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
184 clock-names = "core", "iface";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 status = "disabled";
188 };
189 };
190
191 gsbi6: gsbi@16500000 {
192 compatible = "qcom,gsbi-v1.0.0";
193 cell-index = <12>;
194 reg = <0x16500000 0x100>;
195 clocks = <&gcc GSBI6_H_CLK>;
196 clock-names = "iface";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges;
200 status = "disabled";
201
202 syscon-tcsr = <&tcsr>;
203
204 gsbi6_serial: serial@16540000 {
205 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
206 reg = <0x16540000 0x1000>,
207 <0x16500000 0x1000>;
208 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
210 clock-names = "core", "iface";
211 status = "disabled";
212 };
213
214 gsbi6_i2c: i2c@16580000 {
215 compatible = "qcom,i2c-qup-v1.1.1";
216 reg = <0x16580000 0x1000>;
217 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
219 clock-names = "core", "iface";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 status = "disabled";
223 };
224 };
225
226 gsbi7: gsbi@16600000 {
227 compatible = "qcom,gsbi-v1.0.0";
228 cell-index = <12>;
229 reg = <0x16600000 0x100>;
230 clocks = <&gcc GSBI7_H_CLK>;
231 clock-names = "iface";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
235 status = "disabled";
236
237 syscon-tcsr = <&tcsr>;
238
239 gsbi7_serial: serial@16640000 {
240 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
241 reg = <0x16640000 0x1000>,
242 <0x16600000 0x1000>;
243 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
245 clock-names = "core", "iface";
246 status = "disabled";
247 };
248
249 gsbi7_i2c: i2c@16680000 {
250 compatible = "qcom,i2c-qup-v1.1.1";
251 reg = <0x16680000 0x1000>;
252 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
254 clock-names = "core", "iface";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 status = "disabled";
258 };
259 };
260
261 gsbi8: gsbi@19800000 {
262 compatible = "qcom,gsbi-v1.0.0";
263 cell-index = <12>;
264 reg = <0x19800000 0x100>;
265 clocks = <&gcc GSBI8_H_CLK>;
266 clock-names = "iface";
267 #address-cells = <1>;
268 #size-cells = <1>;
269 ranges;
270
271 syscon-tcsr = <&tcsr>;
272 status = "disabled";
273
274 gsbi8_i2c: i2c@19880000 {
275 compatible = "qcom,i2c-qup-v1.1.1";
276 reg = <0x19880000 0x1000>;
277 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
279 clock-names = "core", "iface";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 };
284 };
285
286 gsbi12: gsbi@19c00000 {
287 compatible = "qcom,gsbi-v1.0.0";
288 cell-index = <12>;
289 reg = <0x19c00000 0x100>;
290 clocks = <&gcc GSBI12_H_CLK>;
291 clock-names = "iface";
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges;
295
296 syscon-tcsr = <&tcsr>;
297
298 gsbi12_serial: serial@19c40000 {
299 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
300 reg = <0x19c40000 0x1000>,
301 <0x19c00000 0x1000>;
302 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
304 clock-names = "core", "iface";
305 status = "disabled";
306 };
307
308 gsbi12_i2c: i2c@19c80000 {
309 compatible = "qcom,i2c-qup-v1.1.1";
310 reg = <0x19c80000 0x1000>;
311 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
313 clock-names = "core", "iface";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318 };
319
320 ebi2: external-bus@1a100000 {
321 compatible = "qcom,msm8660-ebi2";
322 #address-cells = <2>;
323 #size-cells = <1>;
324 ranges = <0 0x0 0x1a800000 0x00800000>,
325 <1 0x0 0x1b000000 0x00800000>,
326 <2 0x0 0x1b800000 0x00800000>,
327 <3 0x0 0x1d000000 0x08000000>,
328 <4 0x0 0x1c800000 0x00800000>,
329 <5 0x0 0x1c000000 0x00800000>;
330 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
331 reg-names = "ebi2", "xmem";
332 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
333 clock-names = "ebi2x", "ebi2";
334 status = "disabled";
335 };
336
337 ssbi@500000 {
338 compatible = "qcom,ssbi";
339 reg = <0x500000 0x1000>;
340 qcom,controller-type = "pmic-arbiter";
341
342 pm8058: pmic {
343 compatible = "qcom,pm8058";
344 interrupt-parent = <&tlmm>;
345 interrupts = <88 8>;
346 #interrupt-cells = <2>;
347 interrupt-controller;
348 #address-cells = <1>;
349 #size-cells = <0>;
350
351 pm8058_gpio: gpio@150 {
352 compatible = "qcom,pm8058-gpio",
353 "qcom,ssbi-gpio";
354 reg = <0x150>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 gpio-controller;
358 gpio-ranges = <&pm8058_gpio 0 0 44>;
359 #gpio-cells = <2>;
360
361 };
362
363 pm8058_mpps: mpps@50 {
364 compatible = "qcom,pm8058-mpp",
365 "qcom,ssbi-mpp";
366 reg = <0x50>;
367 gpio-controller;
368 #gpio-cells = <2>;
369 gpio-ranges = <&pm8058_mpps 0 0 12>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 pwrkey@1c {
375 compatible = "qcom,pm8058-pwrkey";
376 reg = <0x1c>;
377 interrupt-parent = <&pm8058>;
378 interrupts = <50 1>, <51 1>;
379 debounce = <15625>;
380 pull-up;
381 };
382
383 pm8058_keypad: keypad@148 {
384 compatible = "qcom,pm8058-keypad";
385 reg = <0x148>;
386 interrupt-parent = <&pm8058>;
387 interrupts = <74 1>, <75 1>;
388 debounce = <15>;
389 scan-delay = <32>;
390 row-hold = <91500>;
391 };
392
393 xoadc: xoadc@197 {
394 compatible = "qcom,pm8058-adc";
395 reg = <0x197>;
396 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
397 #address-cells = <2>;
398 #size-cells = <0>;
399 #io-channel-cells = <2>;
400
401 vcoin: adc-channel@0 {
402 reg = <0x00 0x00>;
403 };
404 vbat: adc-channel@1 {
405 reg = <0x00 0x01>;
406 };
407 dcin: adc-channel@2 {
408 reg = <0x00 0x02>;
409 };
410 ichg: adc-channel@3 {
411 reg = <0x00 0x03>;
412 };
413 vph_pwr: adc-channel@4 {
414 reg = <0x00 0x04>;
415 };
416 usb_vbus: adc-channel@a {
417 reg = <0x00 0x0a>;
418 };
419 die_temp: adc-channel@b {
420 reg = <0x00 0x0b>;
421 };
422 ref_625mv: adc-channel@c {
423 reg = <0x00 0x0c>;
424 };
425 ref_1250mv: adc-channel@d {
426 reg = <0x00 0x0d>;
427 };
428 ref_325mv: adc-channel@e {
429 reg = <0x00 0x0e>;
430 };
431 ref_muxoff: adc-channel@f {
432 reg = <0x00 0x0f>;
433 };
434 };
435
436 rtc@1e8 {
437 compatible = "qcom,pm8058-rtc";
438 reg = <0x1e8>;
439 interrupt-parent = <&pm8058>;
440 interrupts = <39 1>;
441 allow-set-time;
442 };
443
444 vibrator@4a {
445 compatible = "qcom,pm8058-vib";
446 reg = <0x4a>;
447 };
448
449 pm8058_led48: led@48 {
450 compatible = "qcom,pm8058-keypad-led";
451 reg = <0x48>;
452 status = "disabled";
453 };
454
455 pm8058_led131: led@131 {
456 compatible = "qcom,pm8058-led";
457 reg = <0x131>;
458 status = "disabled";
459 };
460
461 pm8058_led132: led@132 {
462 compatible = "qcom,pm8058-led";
463 reg = <0x132>;
464 status = "disabled";
465 };
466
467 pm8058_led133: led@133 {
468 compatible = "qcom,pm8058-led";
469 reg = <0x133>;
470 status = "disabled";
471 };
472
473 };
474 };
475
476 l2cc: clock-controller@2082000 {
477 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
478 reg = <0x02082000 0x1000>;
479 };
480
481 rpm: rpm@104000 {
482 compatible = "qcom,rpm-msm8660";
483 reg = <0x00104000 0x1000>;
484 qcom,ipc = <&l2cc 0x8 2>;
485
486 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
487 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
488 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
489 interrupt-names = "ack", "err", "wakeup";
490 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
491 clock-names = "ram";
492
493 rpmcc: clock-controller {
494 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
495 #clock-cells = <1>;
496 clocks = <&pxo_board>;
497 clock-names = "pxo";
498 };
499
500 regulators-0 {
501 compatible = "qcom,rpm-pm8901-regulators";
502
503 pm8901_l0: l0 {};
504 pm8901_l1: l1 {};
505 pm8901_l2: l2 {};
506 pm8901_l3: l3 {};
507 pm8901_l4: l4 {};
508 pm8901_l5: l5 {};
509 pm8901_l6: l6 {};
510
511 /* S0 and S1 Handled as SAW regulators by SPM */
512 pm8901_s2: s2 {};
513 pm8901_s3: s3 {};
514 pm8901_s4: s4 {};
515
516 pm8901_lvs0: lvs0 {};
517 pm8901_lvs1: lvs1 {};
518 pm8901_lvs2: lvs2 {};
519 pm8901_lvs3: lvs3 {};
520
521 pm8901_mvs: mvs {};
522 };
523
524 regulators-1 {
525 compatible = "qcom,rpm-pm8058-regulators";
526
527 pm8058_l0: l0 {};
528 pm8058_l1: l1 {};
529 pm8058_l2: l2 {};
530 pm8058_l3: l3 {};
531 pm8058_l4: l4 {};
532 pm8058_l5: l5 {};
533 pm8058_l6: l6 {};
534 pm8058_l7: l7 {};
535 pm8058_l8: l8 {};
536 pm8058_l9: l9 {};
537 pm8058_l10: l10 {};
538 pm8058_l11: l11 {};
539 pm8058_l12: l12 {};
540 pm8058_l13: l13 {};
541 pm8058_l14: l14 {};
542 pm8058_l15: l15 {};
543 pm8058_l16: l16 {};
544 pm8058_l17: l17 {};
545 pm8058_l18: l18 {};
546 pm8058_l19: l19 {};
547 pm8058_l20: l20 {};
548 pm8058_l21: l21 {};
549 pm8058_l22: l22 {};
550 pm8058_l23: l23 {};
551 pm8058_l24: l24 {};
552 pm8058_l25: l25 {};
553
554 pm8058_s0: s0 {};
555 pm8058_s1: s1 {};
556 pm8058_s2: s2 {};
557 pm8058_s3: s3 {};
558 pm8058_s4: s4 {};
559
560 pm8058_lvs0: lvs0 {};
561 pm8058_lvs1: lvs1 {};
562
563 pm8058_ncp: ncp {};
564 };
565 };
566
567 amba {
568 compatible = "simple-bus";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges;
572 sdcc1: mmc@12400000 {
573 status = "disabled";
574 compatible = "arm,pl18x", "arm,primecell";
575 arm,primecell-periphid = <0x00051180>;
576 reg = <0x12400000 0x8000>;
577 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
579 clock-names = "mclk", "apb_pclk";
580 bus-width = <8>;
581 max-frequency = <48000000>;
582 non-removable;
583 cap-sd-highspeed;
584 cap-mmc-highspeed;
585 };
586
587 sdcc2: mmc@12140000 {
588 status = "disabled";
589 compatible = "arm,pl18x", "arm,primecell";
590 arm,primecell-periphid = <0x00051180>;
591 reg = <0x12140000 0x8000>;
592 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
594 clock-names = "mclk", "apb_pclk";
595 bus-width = <8>;
596 max-frequency = <48000000>;
597 cap-sd-highspeed;
598 cap-mmc-highspeed;
599 };
600
601 sdcc3: mmc@12180000 {
602 compatible = "arm,pl18x", "arm,primecell";
603 arm,primecell-periphid = <0x00051180>;
604 status = "disabled";
605 reg = <0x12180000 0x8000>;
606 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
608 clock-names = "mclk", "apb_pclk";
609 bus-width = <4>;
610 cap-sd-highspeed;
611 cap-mmc-highspeed;
612 max-frequency = <48000000>;
613 no-1-8-v;
614 };
615
616 sdcc4: mmc@121c0000 {
617 compatible = "arm,pl18x", "arm,primecell";
618 arm,primecell-periphid = <0x00051180>;
619 status = "disabled";
620 reg = <0x121c0000 0x8000>;
621 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
623 clock-names = "mclk", "apb_pclk";
624 bus-width = <4>;
625 max-frequency = <48000000>;
626 cap-sd-highspeed;
627 cap-mmc-highspeed;
628 };
629
630 sdcc5: mmc@12200000 {
631 compatible = "arm,pl18x", "arm,primecell";
632 arm,primecell-periphid = <0x00051180>;
633 status = "disabled";
634 reg = <0x12200000 0x8000>;
635 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
637 clock-names = "mclk", "apb_pclk";
638 bus-width = <4>;
639 cap-sd-highspeed;
640 cap-mmc-highspeed;
641 max-frequency = <48000000>;
642 };
643 };
644
645 tcsr: syscon@1a400000 {
646 compatible = "qcom,tcsr-msm8660", "syscon";
647 reg = <0x1a400000 0x100>;
648 };
649 };
650
651};