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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / imx / imx6qdl-skov-cpu.dtsi
blob: 2731faede1cb4dce10cf11f7f141b58b3df69e96 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/leds/common.h>
7
8/ {
9 chosen {
10 stdout-path = &uart2;
11 };
12
13 aliases {
14 can0 = &can1;
15 can1 = &can2;
16 mdio-gpio0 = &mdio;
17 nand = &gpmi;
18 rtc0 = &i2c_rtc;
19 rtc1 = &snvs;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 iio-hwmon {
25 compatible = "iio-hwmon";
26 io-channels = <&adc 0>, /* 24V */
27 <&adc 1>; /* temperature */
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 led-0 {
34 label = "D1";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
36 function = LED_FUNCTION_STATUS;
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
39 };
40
41 led-1 {
42 label = "D2";
43 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
44 default-state = "off";
45 };
46
47 led-2 {
48 label = "D3";
49 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
50 default-state = "on";
51 };
52 };
53
54 mdio: mdio {
55 compatible = "microchip,mdio-smi0";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_mdio>;
58 #address-cells = <1>;
59 #size-cells = <0>;
60 gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
61 <&gpio1 22 GPIO_ACTIVE_HIGH>;
62
63 switch@0 {
64 compatible = "microchip,ksz8873";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_switch>;
67 interrupt-parent = <&gpio3>;
68 interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
69 reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
70 reg = <0>;
71
72 ports {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 ports@0 {
77 reg = <0>;
78 phy-mode = "internal";
79 label = "lan1";
80 };
81
82 ports@1 {
83 reg = <1>;
84 phy-mode = "internal";
85 label = "lan2";
86 };
87
88 ports@2 {
89 reg = <2>;
90 label = "cpu";
91 ethernet = <&fec>;
92 phy-mode = "rmii";
93
94 fixed-link {
95 speed = <100>;
96 full-duplex;
97 };
98 };
99 };
100 };
101
102 };
103
104 clk50m_phy: phy-clock {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <50000000>;
108 clock-output-names = "enet_ref_pad";
109 };
110
111 reg_3v3: regulator-3v3 {
112 compatible = "regulator-fixed";
113 vin-supply = <&reg_5v0>;
114 regulator-name = "3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 };
118
119 reg_5v0: regulator-5v0 {
120 compatible = "regulator-fixed";
121 regulator-name = "5v0";
122 regulator-min-microvolt = <5000000>;
123 regulator-max-microvolt = <5000000>;
124 };
125
126 reg_24v0: regulator-24v0 {
127 compatible = "regulator-fixed";
128 regulator-name = "24v0";
129 regulator-min-microvolt = <24000000>;
130 regulator-max-microvolt = <24000000>;
131 };
132
133 reg_can1_stby: regulator-can1-stby {
134 compatible = "regulator-fixed";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can1_stby>;
137 regulator-name = "can1-3v3";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
141 };
142
143 reg_can2_stby: regulator-can2-stby {
144 compatible = "regulator-fixed";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_can2_stby>;
147 regulator-name = "can2-3v3";
148 regulator-min-microvolt = <3300000>;
149 regulator-max-microvolt = <3300000>;
150 gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
151 };
152
153 reg_tft_vcom: regulator-tft-vcom {
154 compatible = "pwm-regulator";
155 pwms = <&pwm3 0 20000 0>;
156 regulator-name = "tft_vcom";
157 regulator-min-microvolt = <3600000>;
158 regulator-max-microvolt = <3600000>;
159 regulator-always-on;
160 voltage-table = <3600000 26>;
161 };
162
163 reg_vcc_mmc: regulator-vcc-mmc {
164 compatible = "regulator-fixed";
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_vcc_mmc>;
167 vin-supply = <&reg_3v3>;
168 regulator-name = "mmc_vcc_supply";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 regulator-boot-on;
173 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
174 enable-active-high;
175 startup-delay-us = <100>;
176 };
177
178 reg_vcc_mmc_io: regulator-vcc-mmc-io {
179 compatible = "regulator-gpio";
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_vcc_mmc_io>;
182 vin-supply = <&reg_5v0>;
183 regulator-name = "mmc_io_supply";
184 regulator-type = "voltage";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <3300000>;
187 gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
188 enable-active-high;
189 states = <1800000 0x1>, <3300000 0x0>;
190 startup-delay-us = <100>;
191 };
192};
193
194&can1 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_can1>;
197 xceiver-supply = <&reg_can1_stby>;
198 status = "okay";
199};
200
201&can2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_can2>;
204 xceiver-supply = <&reg_can2_stby>;
205 status = "okay";
206};
207
208&ecspi1 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_ecspi1>;
211 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
212 status = "okay";
213
214 flash@0 {
215 compatible = "jedec,spi-nor";
216 spi-max-frequency = <54000000>;
217 reg = <0>;
218 };
219};
220
221&ecspi2 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_ecspi2>;
224 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
225 status = "okay";
226
227 adc: adc@0 {
228 compatible = "microchip,mcp3002";
229 reg = <0>;
230 vref-supply = <&reg_3v3>;
231 spi-max-frequency = <1000000>;
232 #io-channel-cells = <1>;
233 };
234};
235
236&clks {
237 clocks = <&clk50m_phy>;
238 clock-names = "enet_ref_pad";
239 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
240 assigned-clock-parents = <&clk50m_phy>;
241};
242
243&fec {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_enet>;
246 phy-mode = "rmii";
247 phy-supply = <&reg_3v3>;
248 status = "okay";
249
250 fixed-link {
251 speed = <100>;
252 full-duplex;
253 };
254};
255
256&gpmi {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_gpmi_nand>;
259 nand-on-flash-bbt;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 status = "okay";
263};
264
265&i2c3 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_i2c3>;
268 clock-frequency = <400000>;
269 status = "okay";
270
271 i2c_rtc: rtc@51 {
272 compatible = "nxp,pcf85063";
273 reg = <0x51>;
274 quartz-load-femtofarads = <12500>;
275 };
276};
277
278&pwm2 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pwm2>;
281 #pwm-cells = <2>;
282 status = "okay";
283};
284
285&pwm3 {
286 /* used for LCD contrast control */
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_pwm3>;
289 status = "okay";
290};
291
292&uart2 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart2>;
295 status = "okay";
296};
297
298&usbh1 {
299 vbus-supply = <&reg_5v0>;
300 disable-over-current;
301 status = "okay";
302};
303
304/* no usbh2 */
305&usbphynop1 {
306 status = "disabled";
307};
308
309/* no usbh3 */
310&usbphynop2 {
311 status = "disabled";
312};
313
314&usbotg {
315 vbus-supply = <&reg_5v0>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usdhc3 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_usdhc3>;
323 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
324 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
325 cap-power-off-card;
326 full-pwr-cycle;
327 bus-width = <4>;
328 max-frequency = <50000000>;
329 cap-sd-highspeed;
330 sd-uhs-sdr12;
331 sd-uhs-sdr25;
332 sd-uhs-sdr50;
333 sd-uhs-ddr50;
334 mmc-ddr-1_8v;
335 vmmc-supply = <&reg_vcc_mmc>;
336 vqmmc-supply = <&reg_vcc_mmc_io>;
337 status = "okay";
338};
339
340&iomuxc {
341 pinctrl_can1: can1grp {
342 fsl,pins = <
343 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008
344 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000
345 >;
346 };
347
348 pinctrl_can1_stby: can1stbygrp {
349 fsl,pins = <
350 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008
351 >;
352 };
353
354 pinctrl_can2: can2grp {
355 fsl,pins = <
356 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
357 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
358 >;
359 };
360
361 pinctrl_can2_stby: can2stbygrp {
362 fsl,pins = <
363 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008
364 >;
365 };
366
367 pinctrl_ecspi1: ecspi1grp {
368 fsl,pins = <
369 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
370 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1
371 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1
372 /* *no* external pull up */
373 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58
374 >;
375 };
376
377 pinctrl_ecspi2: ecspi2grp {
378 fsl,pins = <
379 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
380 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1
381 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1
382 /* external pull up */
383 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58
384 >;
385 };
386
387 pinctrl_enet: enetgrp {
388 fsl,pins = <
389 /* RMII 50 MHz */
390 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
391 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
392 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
393 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
394 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
395 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
396 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
397 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58
398 /* GPIO for "link active" */
399 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038
400 >;
401 };
402
403 pinctrl_gpmi_nand: gpminandgrp {
404 fsl,pins = <
405 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
406 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
407 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
408 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
409 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
410 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
411 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
412 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
413 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
414 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
415 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
416 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
417 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
418 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
419 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
420 >;
421 };
422
423 pinctrl_i2c3: i2c3grp {
424 fsl,pins = <
425 /* external 10 k pull up */
426 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878
427 /* external 10 k pull up */
428 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878
429 >;
430 };
431
432 pinctrl_mdio: mdiogrp {
433 fsl,pins = <
434 MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1
435 MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1
436 >;
437 };
438
439 pinctrl_pwm2: pwm2grp {
440 fsl,pins = <
441 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58
442 >;
443 };
444
445 pinctrl_pwm3: pwm3grp {
446 fsl,pins = <
447 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58
448 >;
449 };
450
451 pinctrl_switch: switchgrp {
452 fsl,pins = <
453 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0
454 >;
455 };
456
457 pinctrl_uart2: uart2grp {
458 fsl,pins = <
459 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
460 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
461 >;
462 };
463
464 pinctrl_usdhc3: usdhc3grp {
465 fsl,pins = <
466 /* SoC internal pull up required */
467 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
468 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
469 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
470 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
471 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
472 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
473 /* SoC internal pull up required */
474 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040
475 /* SoC internal pull up required */
476 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040
477 >;
478 };
479
480 pinctrl_vcc_mmc: vccmmcgrp {
481 fsl,pins = <
482 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58
483 >;
484 };
485
486 pinctrl_vcc_mmc_io: vccmmciogrp {
487 fsl,pins = <
488 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58
489 >;
490 };
491};