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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / imx / imx6qdl-gw5910.dtsi
blob: 424dc7fcd53352a599a5899c39dc726e99ad8724 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
16 };
17
18 chosen {
19 stdout-path = &uart2;
20 };
21
22 memory@10000000 {
23 device_type = "memory";
24 reg = <0x10000000 0x20000000>;
25 };
26
27 gpio-keys {
28 compatible = "gpio-keys";
29
30 user-pb {
31 label = "user_pb";
32 gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
33 linux,code = <BTN_0>;
34 };
35
36 user-pb1x {
37 label = "user_pb1x";
38 linux,code = <BTN_1>;
39 interrupt-parent = <&gsc>;
40 interrupts = <0>;
41 };
42
43 key-erased {
44 label = "key-erased";
45 linux,code = <BTN_2>;
46 interrupt-parent = <&gsc>;
47 interrupts = <1>;
48 };
49
50 eeprom-wp {
51 label = "eeprom_wp";
52 linux,code = <BTN_3>;
53 interrupt-parent = <&gsc>;
54 interrupts = <2>;
55 };
56
57 tamper {
58 label = "tamper";
59 linux,code = <BTN_4>;
60 interrupt-parent = <&gsc>;
61 interrupts = <5>;
62 };
63
64 switch-hold {
65 label = "switch_hold";
66 linux,code = <BTN_5>;
67 interrupt-parent = <&gsc>;
68 interrupts = <7>;
69 };
70 };
71
72 leds {
73 compatible = "gpio-leds";
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_gpio_leds>;
76
77 led0: led-user1 {
78 label = "user1";
79 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
80 default-state = "on";
81 linux,default-trigger = "heartbeat";
82 };
83
84 led1: led-user2 {
85 label = "user2";
86 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
87 default-state = "off";
88 };
89
90 led2: led-user3 {
91 label = "user3";
92 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
93 default-state = "off";
94 };
95 };
96
97 pps {
98 compatible = "pps-gpio";
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_pps>;
101 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
102 status = "okay";
103 };
104
105 reg_3p3v: regulator-3p3v {
106 compatible = "regulator-fixed";
107 regulator-name = "3P3V";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 regulator-always-on;
111 };
112
113 reg_5p0v: regulator-5p0v {
114 compatible = "regulator-fixed";
115 regulator-name = "5P0V";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
118 regulator-always-on;
119 };
120
121 reg_wl: regulator-wl {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_reg_wl>;
124 compatible = "regulator-fixed";
125 regulator-name = "wl";
126 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
127 startup-delay-us = <100>;
128 enable-active-high;
129 regulator-min-microvolt = <3300000>;
130 regulator-max-microvolt = <3300000>;
131 };
132};
133
134
135&ecspi3 {
136 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi3>;
139 status = "okay";
140};
141
142&fec {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_enet>;
145 phy-mode = "rgmii-id";
146 status = "okay";
147};
148
149&gpmi {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_gpmi_nand>;
152 status = "okay";
153};
154
155&i2c1 {
156 clock-frequency = <100000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c1>;
159 status = "okay";
160
161 gsc: gsc@20 {
162 compatible = "gw,gsc";
163 reg = <0x20>;
164 interrupt-parent = <&gpio1>;
165 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 #size-cells = <0>;
169
170 adc {
171 compatible = "gw,gsc-adc";
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 channel@6 {
176 gw,mode = <0>;
177 reg = <0x06>;
178 label = "temp";
179 };
180
181 channel@8 {
182 gw,mode = <3>;
183 reg = <0x08>;
184 label = "vdd_bat";
185 };
186
187 channel@82 {
188 gw,mode = <2>;
189 reg = <0x82>;
190 label = "vdd_vin";
191 gw,voltage-divider-ohms = <22100 1000>;
192 gw,voltage-offset-microvolt = <800000>;
193 };
194
195 channel@84 {
196 gw,mode = <2>;
197 reg = <0x84>;
198 label = "vdd_5p0";
199 gw,voltage-divider-ohms = <22100 10000>;
200 };
201
202 channel@86 {
203 gw,mode = <2>;
204 reg = <0x86>;
205 label = "vdd_3p3";
206 gw,voltage-divider-ohms = <10000 10000>;
207 };
208
209 channel@88 {
210 gw,mode = <2>;
211 reg = <0x88>;
212 label = "vdd_2p5";
213 gw,voltage-divider-ohms = <10000 10000>;
214 };
215
216 channel@8c {
217 gw,mode = <2>;
218 reg = <0x8c>;
219 label = "vdd_3p0";
220 };
221
222 channel@8e {
223 gw,mode = <2>;
224 reg = <0x8e>;
225 label = "vdd_arm";
226 };
227
228 channel@90 {
229 gw,mode = <2>;
230 reg = <0x90>;
231 label = "vdd_soc";
232 };
233
234 channel@92 {
235 gw,mode = <2>;
236 reg = <0x92>;
237 label = "vdd_1p5";
238 };
239
240 channel@98 {
241 gw,mode = <2>;
242 reg = <0x98>;
243 label = "vdd_1p8";
244 };
245
246 channel@9a {
247 gw,mode = <2>;
248 reg = <0x9a>;
249 label = "vdd_1p0";
250 gw,voltage-divider-ohms = <10000 10000>;
251 };
252
253 channel@9c {
254 gw,mode = <2>;
255 reg = <0x9c>;
256 label = "vdd_an1";
257 gw,voltage-divider-ohms = <10000 10000>;
258 };
259
260 channel@a2 {
261 gw,mode = <2>;
262 reg = <0xa2>;
263 label = "vdd_gsc";
264 gw,voltage-divider-ohms = <10000 10000>;
265 };
266 };
267 };
268
269 gsc_gpio: gpio@23 {
270 compatible = "nxp,pca9555";
271 reg = <0x23>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-parent = <&gsc>;
275 interrupts = <4>;
276 };
277
278 eeprom@50 {
279 compatible = "atmel,24c02";
280 reg = <0x50>;
281 pagesize = <16>;
282 };
283
284 eeprom@51 {
285 compatible = "atmel,24c02";
286 reg = <0x51>;
287 pagesize = <16>;
288 };
289
290 eeprom@52 {
291 compatible = "atmel,24c02";
292 reg = <0x52>;
293 pagesize = <16>;
294 };
295
296 eeprom@53 {
297 compatible = "atmel,24c02";
298 reg = <0x53>;
299 pagesize = <16>;
300 };
301
302 rtc@68 {
303 compatible = "dallas,ds1672";
304 reg = <0x68>;
305 };
306};
307
308&i2c2 {
309 clock-frequency = <100000>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_i2c2>;
312 status = "okay";
313};
314
315&i2c3 {
316 clock-frequency = <100000>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_i2c3>;
319 status = "okay";
320
321 accel@19 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_accel>;
324 compatible = "st,lis2de12";
325 reg = <0x19>;
326 st,drdy-int-pin = <1>;
327 interrupt-parent = <&gpio7>;
328 interrupts = <13 0>;
329 };
330};
331
332&pcie {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_pcie>;
335 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
336 status = "okay";
337};
338
339&pwm2 {
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
342 status = "disabled";
343};
344
345&pwm3 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
348 status = "disabled";
349};
350
351/* off-board RS232 */
352&uart1 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_uart1>;
355 status = "okay";
356};
357
358/* serial console */
359&uart2 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_uart2>;
362 status = "okay";
363};
364
365/* cc1352 */
366&uart3 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_uart3>;
369 uart-has-rtscts;
370 status = "okay";
371};
372
373/* Sterling-LWB Bluetooth */
374&uart4 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
377 uart-has-rtscts;
378 status = "okay";
379
380 bluetooth {
381 compatible = "brcm,bcm4330-bt";
382 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
383 };
384};
385
386/* GPS */
387&uart5 {
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_uart5>;
390 status = "okay";
391};
392
393&usbotg {
394 vbus-supply = <&reg_5p0v>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_usbotg>;
397 disable-over-current;
398 status = "okay";
399};
400
401&usbh1 {
402 status = "okay";
403};
404
405/* Sterling-LWB SDIO WiFi */
406&usdhc2 {
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_usdhc2>;
409 vmmc-supply = <&reg_wl>;
410 non-removable;
411 bus-width = <4>;
412 status = "okay";
413};
414
415&usdhc3 {
416 pinctrl-names = "default", "state_100mhz", "state_200mhz";
417 pinctrl-0 = <&pinctrl_usdhc3>;
418 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
419 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
420 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
421 vmmc-supply = <&reg_3p3v>;
422 status = "okay";
423};
424
425&wdog1 {
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_wdog>;
428 fsl,ext-reset-output;
429};
430
431&iomuxc {
432 pinctrl_accel: accelmuxgrp {
433 fsl,pins = <
434 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
435 >;
436 };
437
438 pinctrl_bten: btengrp {
439 fsl,pins = <
440 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
441 >;
442 };
443
444 pinctrl_ecspi3: escpi3grp {
445 fsl,pins = <
446 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
447 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
448 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
449 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
450 >;
451 };
452
453 pinctrl_enet: enetgrp {
454 fsl,pins = <
455 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
456 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
457 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
458 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
459 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
460 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
461 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
462 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
463 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
464 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
465 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
466 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
467 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
468 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
469 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
470 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
471 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
472 >;
473 };
474
475 pinctrl_gpio_leds: gpioledsgrp {
476 fsl,pins = <
477 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
478 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
479 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
480 >;
481 };
482
483 pinctrl_gpmi_nand: gpminandgrp {
484 fsl,pins = <
485 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
486 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
487 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
488 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
489 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
490 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
491 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
492 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
493 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
494 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
495 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
496 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
497 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
498 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
499 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
500 >;
501 };
502
503 pinctrl_i2c1: i2c1grp {
504 fsl,pins = <
505 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
506 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
507 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
508 >;
509 };
510
511 pinctrl_i2c2: i2c2grp {
512 fsl,pins = <
513 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
514 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
515 >;
516 };
517
518 pinctrl_i2c3: i2c3grp {
519 fsl,pins = <
520 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
521 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
522 >;
523 };
524
525 pinctrl_pcie: pciegrp {
526 fsl,pins = <
527 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
528 >;
529 };
530
531 pinctrl_pps: ppsgrp {
532 fsl,pins = <
533 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
534 >;
535 };
536
537 pinctrl_pwm2: pwm2grp {
538 fsl,pins = <
539 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
540 >;
541 };
542
543 pinctrl_pwm3: pwm3grp {
544 fsl,pins = <
545 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
546 >;
547 };
548
549 pinctrl_reg_wl: regwlgrp {
550 fsl,pins = <
551 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
552 >;
553 };
554
555 pinctrl_uart1: uart1grp {
556 fsl,pins = <
557 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
558 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
559 >;
560 };
561
562 pinctrl_uart2: uart2grp {
563 fsl,pins = <
564 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
565 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
566 >;
567 };
568
569 pinctrl_uart3: uart3grp {
570 fsl,pins = <
571 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
572 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
573 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
574 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
575 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
576 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
577 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
578 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
579 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
580 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
581 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
582 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
583 >;
584 };
585
586 pinctrl_uart4: uart4grp {
587 fsl,pins = <
588 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
589 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
590 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
591 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
592 >;
593 };
594
595 pinctrl_uart5: uart5grp {
596 fsl,pins = <
597 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
598 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
599 >;
600 };
601
602 pinctrl_usbotg: usbotggrp {
603 fsl,pins = <
604 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
605 >;
606 };
607
608 pinctrl_usdhc2: usdhc2grp {
609 fsl,pins = <
610 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
611 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
612 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
613 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
614 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
615 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
616 >;
617 };
618
619 pinctrl_usdhc3: usdhc3grp {
620 fsl,pins = <
621 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
622 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
623 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
624 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
625 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
626 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
627 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
628 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
629 >;
630 };
631
632 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
633 fsl,pins = <
634 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
635 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
636 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
637 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
638 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
639 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
640 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
641 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
642 >;
643 };
644
645 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
646 fsl,pins = <
647 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
648 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
649 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
650 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
651 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
652 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
653 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
654 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
655 >;
656 };
657
658 pinctrl_wdog: wdoggrp {
659 fsl,pins = <
660 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
661 >;
662 };
663};