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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / imx / imx6q-tbs2910.dts
blob: 7c298d9aa21e10f4ae445a0f701630dc0192b5f8 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2014 Soeren Moch <smoch@web.de>
4
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 model = "TBS2910 Matrix ARM mini PC";
13 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 aliases {
20 mmc0 = &usdhc2;
21 mmc1 = &usdhc3;
22 mmc2 = &usdhc4;
23 /delete-property/ mmc3;
24 };
25
26 memory@10000000 {
27 device_type = "memory";
28 reg = <0x10000000 0x80000000>;
29 };
30
31 fan {
32 compatible = "gpio-fan";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_fan>;
35 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
36 gpio-fan,speed-map = <0 0
37 3000 1>;
38 };
39
40 ir_recv {
41 compatible = "gpio-ir-receiver";
42 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_ir>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_leds>;
51
52 led-blue {
53 label = "blue_status_led";
54 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
55 default-state = "keep";
56 };
57 };
58
59 reg_2p5v: regulator-2p5v {
60 compatible = "regulator-fixed";
61 regulator-name = "2P5V";
62 regulator-min-microvolt = <2500000>;
63 regulator-max-microvolt = <2500000>;
64 };
65
66 reg_3p3v: regulator-3p3v {
67 compatible = "regulator-fixed";
68 regulator-name = "3P3V";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 };
72
73 reg_5p0v: regulator-5p0v {
74 compatible = "regulator-fixed";
75 regulator-name = "5P0V";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 };
79
80 sound-sgtl5000 {
81 audio-codec = <&sgtl5000>;
82 audio-routing =
83 "MIC_IN", "Mic Jack",
84 "Mic Jack", "Mic Bias",
85 "Headphone Jack", "HP_OUT";
86 compatible = "fsl,imx-audio-sgtl5000";
87 model = "On-board Codec";
88 mux-ext-port = <3>;
89 mux-int-port = <1>;
90 ssi-controller = <&ssi1>;
91 };
92
93 sound-spdif {
94 compatible = "fsl,imx-audio-spdif";
95 model = "On-board SPDIF";
96 spdif-controller = <&spdif>;
97 spdif-out;
98 };
99};
100
101&audmux {
102 status = "okay";
103};
104
105&fec {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet>;
108 phy-mode = "rgmii-id";
109 phy-handle = <&phy>;
110 status = "okay";
111
112 mdio {
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 phy: ethernet-phy@4 {
117 reg = <4>;
118 qca,clk-out-frequency = <125000000>;
119 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
120 reset-assert-us = <10000>;
121 };
122 };
123};
124
125&hdmi {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_hdmi>;
128 ddc-i2c-bus = <&i2c2>;
129 status = "okay";
130};
131
132&i2c1 {
133 clock-frequency = <100000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c1>;
136 status = "okay";
137
138 sgtl5000: sgtl5000@a {
139 clocks = <&clks IMX6QDL_CLK_CKO>;
140 compatible = "fsl,sgtl5000";
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_sgtl5000>;
143 reg = <0x0a>;
144 #sound-dai-cells = <0>;
145 VDDA-supply = <&reg_2p5v>;
146 VDDIO-supply = <&reg_3p3v>;
147 };
148};
149
150&i2c2 {
151 clock-frequency = <100000>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c2>;
154 status = "okay";
155};
156
157&i2c3 {
158 clock-frequency = <100000>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c3>;
161 status = "okay";
162
163 rtc: rtc@68 {
164 compatible = "dallas,ds1307";
165 reg = <0x68>;
166 };
167};
168
169&pcie {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_pcie>;
172 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
173 status = "okay";
174};
175
176&sata {
177 fsl,transmit-level-mV = <1104>;
178 fsl,transmit-boost-mdB = <3330>;
179 fsl,transmit-atten-16ths = <16>;
180 fsl,receive-eq-mdB = <3000>;
181 status = "okay";
182};
183
184&snvs_poweroff {
185 status = "okay";
186};
187
188&spdif {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_spdif>;
191 status = "okay";
192};
193
194&ssi1 {
195 status = "okay";
196};
197
198&uart1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_uart1>;
201 status = "okay";
202};
203
204&uart2 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart2>;
207 status = "okay";
208};
209
210&usbh1 {
211 vbus-supply = <&reg_5p0v>;
212 status = "okay";
213};
214
215&usbotg {
216 vbus-supply = <&reg_5p0v>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_usbotg>;
219 disable-over-current;
220 status = "okay";
221};
222
223&usdhc2 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_usdhc2>;
226 bus-width = <4>;
227 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
228 vmmc-supply = <&reg_3p3v>;
229 vqmmc-supply = <&reg_3p3v>;
230 voltage-ranges = <3300 3300>;
231 no-1-8-v;
232 status = "okay";
233};
234
235&usdhc3 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_usdhc3>;
238 bus-width = <4>;
239 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
240 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
241 vmmc-supply = <&reg_3p3v>;
242 vqmmc-supply = <&reg_3p3v>;
243 voltage-ranges = <3300 3300>;
244 no-1-8-v;
245 status = "okay";
246};
247
248&usdhc4 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_usdhc4>;
251 bus-width = <8>;
252 vmmc-supply = <&reg_3p3v>;
253 vqmmc-supply = <&reg_3p3v>;
254 voltage-ranges = <3300 3300>;
255 non-removable;
256 no-1-8-v;
257 status = "okay";
258};
259
260&iomuxc {
261 pinctrl_enet: enetgrp {
262 fsl,pins = <
263 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
264 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
265 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
266 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
267 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
268 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
269 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
270 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
271 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
272 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
273 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
274 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
275 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
276 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
277 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
278 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
279 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
280 >;
281 };
282
283 pinctrl_gpio_fan: gpiofangrp {
284 fsl,pins = <
285 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
286 >;
287 };
288
289 pinctrl_gpio_leds: gpioledsgrp {
290 fsl,pins = <
291 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
292 >;
293 };
294
295 pinctrl_hdmi: hdmigrp {
296 fsl,pins = <
297 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
298 >;
299 };
300
301 pinctrl_i2c1: i2c1grp {
302 fsl,pins = <
303 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
304 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
305 >;
306 };
307
308 pinctrl_i2c2: i2c2grp {
309 fsl,pins = <
310 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
311 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
312 >;
313 };
314
315 pinctrl_i2c3: i2c3grp {
316 fsl,pins = <
317 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
318 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
319 >;
320 };
321
322 pinctrl_ir: irgrp {
323 fsl,pins = <
324 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
325 >;
326 };
327
328 pinctrl_pcie: pciegrp {
329 fsl,pins = <
330 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
331 >;
332 };
333
334 pinctrl_sgtl5000: sgtl5000grp {
335 fsl,pins = <
336 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
337 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
338 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
339 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
340 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
341 >;
342 };
343
344 pinctrl_spdif: spdifgrp {
345 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
346 >;
347 };
348
349 pinctrl_uart1: uart1grp {
350 fsl,pins = <
351 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
352 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
353 >;
354 };
355
356 pinctrl_uart2: uart2grp {
357 fsl,pins = <
358 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
359 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
360 >;
361 };
362
363 pinctrl_usbotg: usbotggrp {
364 fsl,pins = <
365 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
366 >;
367 };
368
369 pinctrl_usdhc2: usdhc2grp {
370 fsl,pins = <
371 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
372 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
373 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
374 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
375 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
376 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
377 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
378 >;
379 };
380
381 pinctrl_usdhc3: usdhc3grp {
382 fsl,pins = <
383 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
384 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
385 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
386 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
387 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
388 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
389 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
390 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
391 >;
392 };
393
394 pinctrl_usdhc4: usdhc4grp {
395 fsl,pins = <
396 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
397 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
398 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
399 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
400 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
401 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
402 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
403 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
404 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
405 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
406 >;
407 };
408};