| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Xilinx SuperSpeed DWC3 USB SoC controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Piyush Mehta <piyush.mehta@amd.com> |
| 11 | |
| 12 | properties: |
| 13 | compatible: |
| 14 | items: |
| 15 | - enum: |
| 16 | - xlnx,zynqmp-dwc3 |
| 17 | - xlnx,versal-dwc3 |
| 18 | reg: |
| 19 | maxItems: 1 |
| 20 | |
| 21 | "#address-cells": |
| 22 | enum: [ 1, 2 ] |
| 23 | |
| 24 | "#size-cells": |
| 25 | enum: [ 1, 2 ] |
| 26 | |
| 27 | ranges: true |
| 28 | |
| 29 | power-domains: |
| 30 | description: specifies a phandle to PM domain provider node |
| 31 | maxItems: 1 |
| 32 | |
| 33 | clocks: |
| 34 | description: |
| 35 | A list of phandle and clock-specifier pairs for the clocks |
| 36 | listed in clock-names. |
| 37 | items: |
| 38 | - description: Master/Core clock, has to be >= 125 MHz |
| 39 | for SS operation and >= 60MHz for HS operation. |
| 40 | - description: Clock source to core during PHY power down. |
| 41 | |
| 42 | clock-names: |
| 43 | items: |
| 44 | - const: bus_clk |
| 45 | - const: ref_clk |
| 46 | |
| 47 | resets: |
| 48 | description: |
| 49 | A list of phandles for resets listed in reset-names. |
| 50 | |
| 51 | items: |
| 52 | - description: USB core reset |
| 53 | - description: USB hibernation reset |
| 54 | - description: USB APB reset |
| 55 | |
| 56 | reset-names: |
| 57 | items: |
| 58 | - const: usb_crst |
| 59 | - const: usb_hibrst |
| 60 | - const: usb_apbrst |
| 61 | |
| 62 | phys: |
| 63 | minItems: 1 |
| 64 | maxItems: 2 |
| 65 | |
| 66 | phy-names: |
| 67 | minItems: 1 |
| 68 | maxItems: 2 |
| 69 | items: |
| 70 | enum: |
| 71 | - usb2-phy |
| 72 | - usb3-phy |
| 73 | |
| 74 | reset-gpios: |
| 75 | description: GPIO used for the reset ulpi-phy |
| 76 | maxItems: 1 |
| 77 | |
| 78 | # Required child node: |
| 79 | |
| 80 | patternProperties: |
| 81 | "^usb@[0-9a-f]+$": |
| 82 | $ref: snps,dwc3.yaml# |
| 83 | |
| 84 | required: |
| 85 | - compatible |
| 86 | - reg |
| 87 | - "#address-cells" |
| 88 | - "#size-cells" |
| 89 | - ranges |
| 90 | - power-domains |
| 91 | - clocks |
| 92 | - clock-names |
| 93 | - resets |
| 94 | - reset-names |
| 95 | |
| 96 | additionalProperties: false |
| 97 | |
| 98 | examples: |
| 99 | - | |
| 100 | #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> |
| 101 | #include <dt-bindings/power/xlnx-zynqmp-power.h> |
| 102 | #include <dt-bindings/reset/xlnx-zynqmp-resets.h> |
| 103 | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> |
| 104 | #include <dt-bindings/reset/xlnx-zynqmp-resets.h> |
| 105 | #include <dt-bindings/phy/phy.h> |
| 106 | axi { |
| 107 | #address-cells = <2>; |
| 108 | #size-cells = <2>; |
| 109 | |
| 110 | usb@0 { |
| 111 | #address-cells = <0x2>; |
| 112 | #size-cells = <0x2>; |
| 113 | compatible = "xlnx,zynqmp-dwc3"; |
| 114 | reg = <0x0 0xff9d0000 0x0 0x100>; |
| 115 | clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; |
| 116 | clock-names = "bus_clk", "ref_clk"; |
| 117 | power-domains = <&zynqmp_firmware PD_USB_0>; |
| 118 | resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, |
| 119 | <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, |
| 120 | <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; |
| 121 | reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; |
| 122 | phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; |
| 123 | phy-names = "usb3-phy"; |
| 124 | ranges; |
| 125 | |
| 126 | usb@fe200000 { |
| 127 | compatible = "snps,dwc3"; |
| 128 | reg = <0x0 0xfe200000 0x0 0x40000>; |
| 129 | interrupt-names = "host", "otg"; |
| 130 | interrupts = <0 65 4>, <0 69 4>; |
| 131 | dr_mode = "host"; |
| 132 | dma-coherent; |
| 133 | }; |
| 134 | }; |
| 135 | }; |