| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek PWM Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - John Crispin <john@phrozen.org> |
| 11 | |
| 12 | allOf: |
| 13 | - $ref: pwm.yaml# |
| 14 | |
| 15 | properties: |
| 16 | compatible: |
| 17 | oneOf: |
| 18 | - enum: |
| 19 | - mediatek,mt2712-pwm |
| 20 | - mediatek,mt6795-pwm |
| 21 | - mediatek,mt7622-pwm |
| 22 | - mediatek,mt7623-pwm |
| 23 | - mediatek,mt7628-pwm |
| 24 | - mediatek,mt7629-pwm |
| 25 | - mediatek,mt7981-pwm |
| 26 | - mediatek,mt7986-pwm |
| 27 | - mediatek,mt8183-pwm |
| 28 | - mediatek,mt8365-pwm |
| 29 | - mediatek,mt8516-pwm |
| 30 | - items: |
| 31 | - enum: |
| 32 | - mediatek,mt8195-pwm |
| 33 | - const: mediatek,mt8183-pwm |
| 34 | |
| 35 | reg: |
| 36 | maxItems: 1 |
| 37 | |
| 38 | "#pwm-cells": |
| 39 | const: 2 |
| 40 | |
| 41 | interrupts: |
| 42 | maxItems: 1 |
| 43 | |
| 44 | clocks: |
| 45 | minItems: 2 |
| 46 | maxItems: 10 |
| 47 | |
| 48 | clock-names: |
| 49 | description: |
| 50 | This controller needs two input clocks for its core and one |
| 51 | clock for each PWM output. |
| 52 | minItems: 2 |
| 53 | items: |
| 54 | - const: top |
| 55 | - const: main |
| 56 | - const: pwm1 |
| 57 | - const: pwm2 |
| 58 | - const: pwm3 |
| 59 | - const: pwm4 |
| 60 | - const: pwm5 |
| 61 | - const: pwm6 |
| 62 | - const: pwm7 |
| 63 | - const: pwm8 |
| 64 | |
| 65 | required: |
| 66 | - compatible |
| 67 | - reg |
| 68 | - "#pwm-cells" |
| 69 | - clocks |
| 70 | - clock-names |
| 71 | |
| 72 | additionalProperties: false |
| 73 | |
| 74 | examples: |
| 75 | - | |
| 76 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 77 | #include <dt-bindings/clock/mt2712-clk.h> |
| 78 | #include <dt-bindings/interrupt-controller/irq.h> |
| 79 | |
| 80 | pwm0: pwm@11006000 { |
| 81 | compatible = "mediatek,mt2712-pwm"; |
| 82 | reg = <0x11006000 0x1000>; |
| 83 | #pwm-cells = <2>; |
| 84 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; |
| 85 | clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>, |
| 86 | <&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>, |
| 87 | <&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>, |
| 88 | <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>, |
| 89 | <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>; |
| 90 | clock-names = "top", "main", |
| 91 | "pwm1", "pwm2", |
| 92 | "pwm3", "pwm4", |
| 93 | "pwm5", "pwm6", |
| 94 | "pwm7", "pwm8"; |
| 95 | }; |