Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | title: Qualcomm Technologies, Inc. SM6125 TLMM block |
| 7 | |
| 8 | maintainers: |
| 9 | - Martin Botka <martin.botka@somainline.org> |
| 10 | |
| 11 | description: |
| 12 | Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC. |
| 13 | |
| 14 | allOf: |
| 15 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | const: qcom,sm6125-tlmm |
| 20 | |
| 21 | reg: |
| 22 | maxItems: 3 |
| 23 | |
| 24 | reg-names: |
| 25 | items: |
| 26 | - const: west |
| 27 | - const: south |
| 28 | - const: east |
| 29 | |
| 30 | interrupts: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | interrupt-controller: true |
| 34 | "#interrupt-cells": true |
| 35 | gpio-controller: true |
| 36 | gpio-reserved-ranges: true |
| 37 | "#gpio-cells": true |
| 38 | gpio-ranges: true |
| 39 | wakeup-parent: true |
| 40 | |
| 41 | required: |
| 42 | - compatible |
| 43 | - reg |
| 44 | - reg-names |
| 45 | |
| 46 | additionalProperties: false |
| 47 | |
| 48 | patternProperties: |
| 49 | "-state$": |
| 50 | oneOf: |
| 51 | - $ref: "#/$defs/qcom-sm6125-tlmm-state" |
| 52 | - patternProperties: |
| 53 | "-pins$": |
| 54 | $ref: "#/$defs/qcom-sm6125-tlmm-state" |
| 55 | additionalProperties: false |
| 56 | |
| 57 | $defs: |
| 58 | qcom-sm6125-tlmm-state: |
| 59 | type: object |
| 60 | description: |
| 61 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 62 | Client device subnodes use below standard properties. |
| 63 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 64 | unevaluatedProperties: false |
| 65 | |
| 66 | properties: |
| 67 | pins: |
| 68 | description: |
| 69 | List of gpio pins affected by the properties specified in this |
| 70 | subnode. |
| 71 | items: |
| 72 | oneOf: |
| 73 | - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" |
| 74 | - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] |
| 75 | minItems: 1 |
| 76 | maxItems: 36 |
| 77 | |
| 78 | function: |
| 79 | description: |
| 80 | Specify the alternative function to be configured for the specified |
| 81 | pins. |
| 82 | |
| 83 | enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, |
| 84 | atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, |
| 85 | atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, |
| 86 | atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, |
| 87 | audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, |
| 88 | cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, |
| 89 | cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, |
| 90 | ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, |
| 91 | dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, |
| 92 | gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, |
| 93 | ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, |
| 94 | mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, |
| 95 | nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, |
| 96 | pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, |
| 97 | qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, |
| 98 | qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, |
| 99 | swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, |
| 100 | uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, |
| 101 | uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, |
| 102 | wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] |
| 103 | |
| 104 | |
| 105 | required: |
| 106 | - pins |
| 107 | |
| 108 | examples: |
| 109 | - | |
| 110 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 111 | pinctrl@500000 { |
| 112 | compatible = "qcom,sm6125-tlmm"; |
| 113 | reg = <0x00500000 0x400000>, |
| 114 | <0x00900000 0x400000>, |
| 115 | <0x00d00000 0x400000>; |
| 116 | reg-names = "west", "south", "east"; |
| 117 | interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| 118 | gpio-controller; |
| 119 | gpio-ranges = <&tlmm 0 0 134>; |
| 120 | #gpio-cells = <2>; |
| 121 | interrupt-controller; |
| 122 | #interrupt-cells = <2>; |
| 123 | |
| 124 | sdc2-off-state { |
| 125 | clk-pins { |
| 126 | pins = "sdc2_clk"; |
| 127 | drive-strength = <2>; |
| 128 | bias-disable; |
| 129 | }; |
| 130 | |
| 131 | cmd-pins { |
| 132 | pins = "sdc2_cmd"; |
| 133 | drive-strength = <2>; |
| 134 | bias-pull-up; |
| 135 | }; |
| 136 | |
| 137 | data-pins { |
| 138 | pins = "sdc2_data"; |
| 139 | drive-strength = <2>; |
| 140 | bias-pull-up; |
| 141 | }; |
| 142 | }; |
| 143 | }; |