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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / pinctrl / qcom,sc8280xp-lpass-lpi-pinctrl.yaml
blob: a9167dac9ab58b239c226df894238bbbbb9fa737 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC8280XP SoC LPASS LPI TLMM
8
9maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
12description:
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
15
16properties:
17 compatible:
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
19
20 reg:
21 items:
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
24
25 clocks:
26 items:
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
29
30 clock-names:
31 items:
32 - const: core
33 - const: audio
34
35 gpio-controller: true
36
37 "#gpio-cells":
38 description: Specifying the pin number and flags, as defined in
39 include/dt-bindings/gpio/gpio.h
40 const: 2
41
42 gpio-ranges:
43 maxItems: 1
44
45patternProperties:
46 "-state$":
47 oneOf:
48 - $ref: "#/$defs/qcom-sc8280xp-lpass-state"
49 - patternProperties:
50 "-pins$":
51 $ref: "#/$defs/qcom-sc8280xp-lpass-state"
52 additionalProperties: false
53
54$defs:
55 qcom-sc8280xp-lpass-state:
56 type: object
57 description:
58 Pinctrl node's client devices use subnodes for desired pin configuration.
59 Client device subnodes use below standard properties.
60 $ref: /schemas/pinctrl/pincfg-node.yaml
61
62 properties:
63 pins:
64 description:
65 List of gpio pins affected by the properties specified in this
66 subnode.
67 items:
68 pattern: "^gpio([0-9]|1[0-8])$"
69
70 function:
71 enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
72 dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
73 dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
74 qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
75 i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
76 wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
77 ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
78 description:
79 Specify the alternative function to be configured for the specified
80 pins.
81
82 drive-strength:
83 enum: [2, 4, 6, 8, 10, 12, 14, 16]
84 default: 2
85 description:
86 Selects the drive strength for the specified pins, in mA.
87
88 slew-rate:
89 enum: [0, 1, 2, 3]
90 default: 0
91 description: |
92 0: No adjustments
93 1: Higher Slew rate (faster edges)
94 2: Lower Slew rate (slower edges)
95 3: Reserved (No adjustments)
96
97 bias-bus-hold: true
98 bias-pull-down: true
99 bias-pull-up: true
100 bias-disable: true
101 input-enable: true
102 output-high: true
103 output-low: true
104
105 required:
106 - pins
107 - function
108
109 additionalProperties: false
110
111allOf:
112 - $ref: pinctrl.yaml#
113
114required:
115 - compatible
116 - reg
117 - clocks
118 - clock-names
119 - gpio-controller
120 - "#gpio-cells"
121 - gpio-ranges
122
123additionalProperties: false
124
125examples:
126 - |
127 #include <dt-bindings/sound/qcom,q6afe.h>
128 pinctrl@33c0000 {
129 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
130 reg = <0x33c0000 0x20000>,
131 <0x3550000 0x10000>;
132 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
133 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
134 clock-names = "core", "audio";
135 gpio-controller;
136 #gpio-cells = <2>;
137 gpio-ranges = <&lpi_tlmm 0 0 19>;
138
139 dmic01-state {
140 dmic01-clk-pins {
141 pins = "gpio16";
142 function = "dmic1_clk";
143 };
144
145 dmic01-clk-sleep-pins {
146 pins = "gpio16";
147 function = "dmic1_clk";
148 };
149 };
150
151 tx-swr-data-sleep-state {
152 pins = "gpio0", "gpio1";
153 function = "swr_tx_data";
154 };
155 };