Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm MSM8994 TLMM pin controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Bjorn Andersson <andersson@kernel.org> |
| 11 | - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
| 12 | |
| 13 | description: |
| 14 | Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC. |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | enum: |
| 19 | - qcom,msm8992-pinctrl |
| 20 | - qcom,msm8994-pinctrl |
| 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | interrupts: |
| 26 | maxItems: 1 |
| 27 | |
| 28 | interrupt-controller: true |
| 29 | "#interrupt-cells": true |
| 30 | gpio-controller: true |
| 31 | "#gpio-cells": true |
| 32 | gpio-ranges: true |
| 33 | wakeup-parent: true |
| 34 | |
| 35 | gpio-reserved-ranges: |
| 36 | minItems: 1 |
| 37 | maxItems: 73 |
| 38 | |
| 39 | gpio-line-names: |
| 40 | maxItems: 146 |
| 41 | |
| 42 | patternProperties: |
| 43 | "-state$": |
| 44 | oneOf: |
| 45 | - $ref: "#/$defs/qcom-msm8994-tlmm-state" |
| 46 | - patternProperties: |
| 47 | "-pins$": |
| 48 | $ref: "#/$defs/qcom-msm8994-tlmm-state" |
| 49 | additionalProperties: false |
| 50 | |
| 51 | $defs: |
| 52 | qcom-msm8994-tlmm-state: |
| 53 | type: object |
| 54 | description: |
| 55 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 56 | Client device subnodes use below standard properties. |
| 57 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 58 | unevaluatedProperties: false |
| 59 | |
| 60 | properties: |
| 61 | pins: |
| 62 | description: |
| 63 | List of gpio pins affected by the properties specified in this |
| 64 | subnode. |
| 65 | items: |
| 66 | oneOf: |
| 67 | - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" |
| 68 | - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, |
| 69 | sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] |
| 70 | minItems: 1 |
| 71 | maxItems: 36 |
| 72 | |
| 73 | function: |
| 74 | description: |
| 75 | Specify the alternative function to be configured for the specified |
| 76 | pins. |
| 77 | |
| 78 | enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, |
| 79 | blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, |
| 80 | blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, |
| 81 | blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, |
| 82 | blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, |
| 83 | blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, |
| 84 | blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, |
| 85 | blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, |
| 86 | blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, |
| 87 | blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, |
| 88 | blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, |
| 89 | blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, |
| 90 | blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, |
| 91 | blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1, |
| 92 | cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1, |
| 93 | cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1, |
| 94 | cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a, |
| 95 | gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, |
| 96 | gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, |
| 97 | gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, |
| 98 | hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync, |
| 99 | qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c, |
| 100 | qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b, |
| 101 | qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a, |
| 102 | qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, |
| 103 | qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1, |
| 104 | pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, |
| 105 | tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ] |
| 106 | |
| 107 | required: |
| 108 | - pins |
| 109 | |
| 110 | allOf: |
| 111 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 112 | |
| 113 | required: |
| 114 | - compatible |
| 115 | - reg |
| 116 | |
| 117 | additionalProperties: false |
| 118 | |
| 119 | examples: |
| 120 | - | |
| 121 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 122 | |
| 123 | tlmm: pinctrl@fd510000 { |
| 124 | compatible = "qcom,msm8994-pinctrl"; |
| 125 | reg = <0xfd510000 0x4000>; |
| 126 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 127 | gpio-controller; |
| 128 | gpio-ranges = <&tlmm 0 0 146>; |
| 129 | #gpio-cells = <2>; |
| 130 | interrupt-controller; |
| 131 | #interrupt-cells = <2>; |
| 132 | |
| 133 | blsp1-uart2-default-state { |
| 134 | function = "blsp_uart2"; |
| 135 | pins = "gpio4", "gpio5"; |
| 136 | drive-strength = <16>; |
| 137 | bias-disable; |
| 138 | }; |
| 139 | |
| 140 | blsp1-spi1-default-state { |
| 141 | default-pins { |
| 142 | pins = "gpio0", "gpio1", "gpio3"; |
| 143 | function = "blsp_spi1"; |
| 144 | drive-strength = <10>; |
| 145 | bias-pull-down; |
| 146 | }; |
| 147 | |
| 148 | cs-pins { |
| 149 | pins = "gpio8"; |
| 150 | function = "gpio"; |
| 151 | drive-strength = <2>; |
| 152 | bias-disable; |
| 153 | }; |
| 154 | }; |
| 155 | }; |