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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / phy / allwinner,sun8i-h3-usb-phy.yaml
blob: 2df012d13655ee361e19b2b6e53e2ecc625206d7 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner H3 USB PHY
8
9maintainers:
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
12
13properties:
14 "#phy-cells":
15 const: 1
16
17 compatible:
18 enum:
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
21
22 reg:
23 items:
24 - description: PHY Control registers
25 - description: PHY PMU0 registers
26 - description: PHY PMU1 registers
27 - description: PHY PMU2 registers
28 - description: PHY PMU3 registers
29
30 reg-names:
31 items:
32 - const: phy_ctrl
33 - const: pmu0
34 - const: pmu1
35 - const: pmu2
36 - const: pmu3
37
38 clocks:
39 minItems: 4
40 items:
41 - description: USB OTG PHY bus clock
42 - description: USB Host 0 PHY bus clock
43 - description: USB Host 1 PHY bus clock
44 - description: USB Host 2 PHY bus clock
45 - description: PMU clock for host port 2
46
47 clock-names:
48 minItems: 4
49 items:
50 - const: usb0_phy
51 - const: usb1_phy
52 - const: usb2_phy
53 - const: usb3_phy
54 - const: pmu2_clk
55
56 resets:
57 items:
58 - description: USB OTG reset
59 - description: USB Host 1 Controller reset
60 - description: USB Host 2 Controller reset
61 - description: USB Host 3 Controller reset
62
63 reset-names:
64 items:
65 - const: usb0_reset
66 - const: usb1_reset
67 - const: usb2_reset
68 - const: usb3_reset
69
70 usb0_id_det-gpios:
71 maxItems: 1
72 description: GPIO to the USB OTG ID pin
73
74 usb0_vbus_det-gpios:
75 maxItems: 1
76 description: GPIO to the USB OTG VBUS detect pin
77
78 usb0_vbus_power-supply:
79 description: Power supply to detect the USB OTG VBUS
80
81 usb0_vbus-supply:
82 description: Regulator controlling USB OTG VBUS
83
84 usb1_vbus-supply:
85 description: Regulator controlling USB1 Host controller
86
87 usb2_vbus-supply:
88 description: Regulator controlling USB2 Host controller
89
90 usb3_vbus-supply:
91 description: Regulator controlling USB3 Host controller
92
93required:
94 - "#phy-cells"
95 - compatible
96 - clocks
97 - clock-names
98 - reg
99 - reg-names
100 - resets
101 - reset-names
102
103allOf:
104 - if:
105 properties:
106 compatible:
107 contains:
108 enum:
109 - allwinner,sun50i-h616-usb-phy
110 then:
111 properties:
112 clocks:
113 minItems: 5
114
115 clock-names:
116 minItems: 5
117 else:
118 properties:
119 clocks:
120 maxItems: 4
121
122 clock-names:
123 maxItems: 4
124
125additionalProperties: false
126
127examples:
128 - |
129 #include <dt-bindings/gpio/gpio.h>
130 #include <dt-bindings/clock/sun8i-h3-ccu.h>
131 #include <dt-bindings/reset/sun8i-h3-ccu.h>
132
133 phy@1c19400 {
134 #phy-cells = <1>;
135 compatible = "allwinner,sun8i-h3-usb-phy";
136 reg = <0x01c19400 0x2c>,
137 <0x01c1a800 0x4>,
138 <0x01c1b800 0x4>,
139 <0x01c1c800 0x4>,
140 <0x01c1d800 0x4>;
141 reg-names = "phy_ctrl",
142 "pmu0",
143 "pmu1",
144 "pmu2",
145 "pmu3";
146 clocks = <&ccu CLK_USB_PHY0>,
147 <&ccu CLK_USB_PHY1>,
148 <&ccu CLK_USB_PHY2>,
149 <&ccu CLK_USB_PHY3>;
150 clock-names = "usb0_phy",
151 "usb1_phy",
152 "usb2_phy",
153 "usb3_phy";
154 resets = <&ccu RST_USB_PHY0>,
155 <&ccu RST_USB_PHY1>,
156 <&ccu RST_USB_PHY2>,
157 <&ccu RST_USB_PHY3>;
158 reset-names = "usb0_reset",
159 "usb1_reset",
160 "usb2_reset",
161 "usb3_reset";
162 usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
163 usb0_vbus-supply = <&reg_usb0_vbus>;
164 usb1_vbus-supply = <&reg_usb1_vbus>;
165 usb2_vbus-supply = <&reg_usb2_vbus>;
166 usb3_vbus-supply = <&reg_usb3_vbus>;
167 };