| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | # Copyright 2021 Arm Ltd. |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | |
| 8 | title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) |
| 9 | |
| 10 | maintainers: |
| 11 | - Suzuki K Poulose <suzuki.poulose@arm.com> |
| 12 | - Robin Murphy <robin.murphy@arm.com> |
| 13 | |
| 14 | description: |
| 15 | ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared |
| 16 | L3 memory system, control logic and external interfaces to form a multicore |
| 17 | cluster. The PMU enables gathering various statistics on the operation of the |
| 18 | DSU. The PMU provides independent 32-bit counters that can count any of the |
| 19 | supported events, along with a 64-bit cycle counter. The PMU is accessed via |
| 20 | CPU system registers and has no MMIO component. |
| 21 | |
| 22 | properties: |
| 23 | compatible: |
| 24 | oneOf: |
| 25 | - const: arm,dsu-pmu |
| 26 | - items: |
| 27 | - const: arm,dsu-110-pmu |
| 28 | - const: arm,dsu-pmu |
| 29 | |
| 30 | interrupts: |
| 31 | items: |
| 32 | - description: nCLUSTERPMUIRQ interrupt |
| 33 | |
| 34 | cpus: |
| 35 | minItems: 1 |
| 36 | maxItems: 12 |
| 37 | description: List of phandles for the CPUs connected to this DSU instance. |
| 38 | |
| 39 | required: |
| 40 | - compatible |
| 41 | - interrupts |
| 42 | - cpus |
| 43 | |
| 44 | additionalProperties: false |