| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Common properties for LPDDR types |
| 8 | |
| 9 | description: |
| 10 | Different LPDDR types generally use the same properties and only differ in the |
| 11 | range of legal values for each. This file defines the common parts that can be |
| 12 | reused for each type. Nodes using this schema should generally be nested under |
| 13 | an LPDDR channel node. |
| 14 | |
| 15 | maintainers: |
| 16 | - Krzysztof Kozlowski <krzk@kernel.org> |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | description: |
| 21 | Compatible strings can be either explicit vendor names and part numbers |
| 22 | (e.g. elpida,ECB240ABACN), or generated strings of the form |
| 23 | lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID |
| 24 | (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are |
| 25 | formatted in lower case hexadecimal representation with leading zeroes. |
| 26 | The latter form can be useful when LPDDR nodes are created at runtime by |
| 27 | boot firmware that doesn't have access to static part number information. |
| 28 | |
| 29 | reg: |
| 30 | description: |
| 31 | The rank number of this LPDDR rank when used as a subnode to an LPDDR |
| 32 | channel. |
| 33 | minimum: 0 |
| 34 | maximum: 3 |
| 35 | |
| 36 | revision-id: |
| 37 | $ref: /schemas/types.yaml#/definitions/uint32-array |
| 38 | description: |
| 39 | Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>). |
| 40 | maxItems: 2 |
| 41 | items: |
| 42 | minimum: 0 |
| 43 | maximum: 255 |
| 44 | |
| 45 | density: |
| 46 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 47 | description: |
| 48 | Density in megabits of SDRAM chip. Decoded from Mode Register 8. |
| 49 | enum: |
| 50 | - 64 |
| 51 | - 128 |
| 52 | - 256 |
| 53 | - 512 |
| 54 | - 1024 |
| 55 | - 2048 |
| 56 | - 3072 |
| 57 | - 4096 |
| 58 | - 6144 |
| 59 | - 8192 |
| 60 | - 12288 |
| 61 | - 16384 |
| 62 | - 24576 |
| 63 | - 32768 |
| 64 | |
| 65 | io-width: |
| 66 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 67 | description: |
| 68 | IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. |
| 69 | enum: |
| 70 | - 8 |
| 71 | - 16 |
| 72 | - 32 |
| 73 | |
| 74 | additionalProperties: true |