Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/media/samsung,exynos4212-fimc-is.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Samsung Exynos4212/4412 SoC Imaging Subsystem (FIMC-IS) |
| 8 | |
| 9 | maintainers: |
| 10 | - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
| 11 | - Sylwester Nawrocki <s.nawrocki@samsung.com> |
| 12 | |
| 13 | description: |
| 14 | The FIMC-IS is a subsystem for processing image signal from an image sensor. |
| 15 | The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5 |
| 16 | processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C |
| 17 | and SPI bus controllers, PWM and ADC. |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | enum: |
| 22 | - samsung,exynos4212-fimc-is |
| 23 | |
| 24 | reg: |
| 25 | maxItems: 1 |
| 26 | |
| 27 | ranges: true |
| 28 | |
| 29 | '#address-cells': |
| 30 | const: 1 |
| 31 | |
| 32 | '#size-cells': |
| 33 | const: 1 |
| 34 | |
| 35 | clocks: |
| 36 | maxItems: 21 |
| 37 | |
| 38 | clock-names: |
| 39 | items: |
| 40 | - const: lite0 |
| 41 | - const: lite1 |
| 42 | - const: ppmuispx |
| 43 | - const: ppmuispmx |
| 44 | - const: isp |
| 45 | - const: drc |
| 46 | - const: fd |
| 47 | - const: mcuisp |
| 48 | - const: gicisp |
| 49 | - const: mcuctl_isp |
| 50 | - const: pwm_isp |
| 51 | - const: ispdiv0 |
| 52 | - const: ispdiv1 |
| 53 | - const: mcuispdiv0 |
| 54 | - const: mcuispdiv1 |
| 55 | - const: mpll |
| 56 | - const: aclk200 |
| 57 | - const: aclk400mcuisp |
| 58 | - const: div_aclk200 |
| 59 | - const: div_aclk400mcuisp |
| 60 | - const: uart |
| 61 | |
| 62 | interrupts: |
| 63 | maxItems: 2 |
| 64 | |
| 65 | iommus: |
| 66 | maxItems: 4 |
| 67 | |
| 68 | iommu-names: |
| 69 | items: |
| 70 | - const: isp |
| 71 | - const: drc |
| 72 | - const: fd |
| 73 | - const: mcuctl |
| 74 | |
| 75 | power-domains: |
| 76 | maxItems: 1 |
| 77 | |
| 78 | samsung,pmu-syscon: |
| 79 | $ref: /schemas/types.yaml#/definitions/phandle |
| 80 | description: |
| 81 | Power Management Unit (PMU) system controller interface, used to |
| 82 | power/start the ISP. |
| 83 | |
| 84 | patternProperties: |
| 85 | "^pmu@[0-9a-f]+$": |
| 86 | type: object |
| 87 | additionalProperties: false |
| 88 | deprecated: true |
| 89 | description: |
| 90 | Node representing the SoC's Power Management Unit (duplicated with the |
| 91 | correct PMU node in the SoC). Deprecated, use samsung,pmu-syscon. |
| 92 | |
| 93 | properties: |
| 94 | reg: |
| 95 | maxItems: 1 |
| 96 | |
| 97 | required: |
| 98 | - reg |
| 99 | |
| 100 | "^i2c-isp@[0-9a-f]+$": |
| 101 | type: object |
| 102 | $ref: /schemas/i2c/i2c-controller.yaml# |
| 103 | unevaluatedProperties: false |
| 104 | description: |
| 105 | ISP I2C bus controller |
| 106 | |
| 107 | properties: |
| 108 | compatible: |
| 109 | const: samsung,exynos4212-i2c-isp |
| 110 | |
| 111 | reg: |
| 112 | maxItems: 1 |
| 113 | |
| 114 | |
| 115 | clocks: |
| 116 | maxItems: 1 |
| 117 | |
| 118 | clock-names: |
| 119 | items: |
| 120 | - const: i2c_isp |
| 121 | |
| 122 | pinctrl-0: true |
| 123 | pinctrl-names: |
| 124 | items: |
| 125 | - const: default |
| 126 | |
| 127 | required: |
| 128 | - compatible |
| 129 | - reg |
| 130 | - clocks |
| 131 | - clock-names |
| 132 | |
| 133 | required: |
| 134 | - compatible |
| 135 | - reg |
| 136 | - '#address-cells' |
| 137 | - clocks |
| 138 | - clock-names |
| 139 | - interrupts |
| 140 | - ranges |
| 141 | - samsung,pmu-syscon |
| 142 | - '#size-cells' |
| 143 | |
| 144 | additionalProperties: false |
| 145 | |
| 146 | examples: |
| 147 | - | |
| 148 | #include <dt-bindings/clock/exynos4.h> |
| 149 | #include <dt-bindings/gpio/gpio.h> |
| 150 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 151 | |
| 152 | fimc-is@12000000 { |
| 153 | compatible = "samsung,exynos4212-fimc-is"; |
| 154 | reg = <0x12000000 0x260000>; |
| 155 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, |
| 156 | <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| 157 | clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, |
| 158 | <&isp_clock CLK_ISP_FIMC_LITE1>, |
| 159 | <&isp_clock CLK_ISP_PPMUISPX>, |
| 160 | <&isp_clock CLK_ISP_PPMUISPMX>, |
| 161 | <&isp_clock CLK_ISP_FIMC_ISP>, |
| 162 | <&isp_clock CLK_ISP_FIMC_DRC>, |
| 163 | <&isp_clock CLK_ISP_FIMC_FD>, |
| 164 | <&isp_clock CLK_ISP_MCUISP>, |
| 165 | <&isp_clock CLK_ISP_GICISP>, |
| 166 | <&isp_clock CLK_ISP_MCUCTL_ISP>, |
| 167 | <&isp_clock CLK_ISP_PWM_ISP>, |
| 168 | <&isp_clock CLK_ISP_DIV_ISP0>, |
| 169 | <&isp_clock CLK_ISP_DIV_ISP1>, |
| 170 | <&isp_clock CLK_ISP_DIV_MCUISP0>, |
| 171 | <&isp_clock CLK_ISP_DIV_MCUISP1>, |
| 172 | <&clock CLK_MOUT_MPLL_USER_T>, |
| 173 | <&clock CLK_ACLK200>, |
| 174 | <&clock CLK_ACLK400_MCUISP>, |
| 175 | <&clock CLK_DIV_ACLK200>, |
| 176 | <&clock CLK_DIV_ACLK400_MCUISP>, |
| 177 | <&clock CLK_UART_ISP_SCLK>; |
| 178 | clock-names = "lite0", "lite1", "ppmuispx", |
| 179 | "ppmuispmx", "isp", |
| 180 | "drc", "fd", "mcuisp", |
| 181 | "gicisp", "mcuctl_isp", "pwm_isp", |
| 182 | "ispdiv0", "ispdiv1", "mcuispdiv0", |
| 183 | "mcuispdiv1", "mpll", "aclk200", |
| 184 | "aclk400mcuisp", "div_aclk200", |
| 185 | "div_aclk400mcuisp", "uart"; |
| 186 | iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, |
| 187 | <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; |
| 188 | iommu-names = "isp", "drc", "fd", "mcuctl"; |
| 189 | power-domains = <&pd_isp>; |
| 190 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 191 | |
| 192 | #address-cells = <1>; |
| 193 | #size-cells = <1>; |
| 194 | ranges; |
| 195 | |
| 196 | i2c-isp@12140000 { |
| 197 | compatible = "samsung,exynos4212-i2c-isp"; |
| 198 | reg = <0x12140000 0x100>; |
| 199 | clocks = <&isp_clock CLK_ISP_I2C1_ISP>; |
| 200 | clock-names = "i2c_isp"; |
| 201 | pinctrl-0 = <&fimc_is_i2c1>; |
| 202 | pinctrl-names = "default"; |
| 203 | #address-cells = <1>; |
| 204 | #size-cells = <0>; |
| 205 | |
| 206 | image-sensor@10 { |
| 207 | compatible = "samsung,s5k6a3"; |
| 208 | reg = <0x10>; |
| 209 | svdda-supply = <&cam_io_reg>; |
| 210 | svddio-supply = <&ldo19_reg>; |
| 211 | afvdd-supply = <&ldo19_reg>; |
| 212 | clock-frequency = <24000000>; |
| 213 | clocks = <&camera 1>; |
| 214 | clock-names = "extclk"; |
| 215 | gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; |
| 216 | |
| 217 | port { |
| 218 | endpoint { |
| 219 | remote-endpoint = <&csis1_ep>; |
| 220 | data-lanes = <1>; |
| 221 | }; |
| 222 | }; |
| 223 | }; |
| 224 | }; |
| 225 | }; |