Bindings/media/microchip,csi2dc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip CSI2 Demux Controller (CSI2DC)

maintainers:
  - Eugen Hristev <eugen.hristev@microchip.com>

description:
  CSI2DC - Camera Serial Interface 2 Demux Controller

  CSI2DC is a hardware block that receives incoming data from either from an
  IDI interface or from a parallel bus interface.
  It filters IDI packets based on their data type and virtual channel
  identifier, then converts the byte stream to a pixel stream into a cross
  clock domain towards a parallel interface that can be read by a sensor
  controller.
  IDI interface is Synopsys proprietary.
  CSI2DC can act a simple bypass bridge if the incoming data is coming from
  a parallel interface.

  CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
  is connected at the output to a sensor controller and the data pipe is
  accessible as a DMA slave port to a DMA controller.

  CSI2DC supports a single 'port' node as a sink port with either Synopsys
  32-bit IDI interface or a parallel interface.

  CSI2DC supports one 'port' node as source port with parallel interface.
  This is called video pipe.
  This port has an 'endpoint' that can be connected to a sink port of another
  controller (next in pipeline).

  CSI2DC also supports direct access to the data through AHB, via DMA channel,
  called data pipe.
  For data pipe to be available, a dma controller and a dma channel must be
  referenced.

properties:
  compatible:
    const: microchip,sama7g5-csi2dc

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    description:
      CSI2DC must have two clocks to function correctly. One clock is the
      peripheral clock for the inside functionality of the hardware block.
      This is named 'pclk'. The second clock must be the cross domain clock,
      in which CSI2DC will perform clock crossing. This clock must be fed
      by the next controller in pipeline, which usually is a sensor controller.
      Normally this clock should be given by this sensor controller who
      is also a clock source. This clock is named 'scck', sensor controller clock.
    items:
      - const: pclk
      - const: scck

  dmas:
    maxItems: 1

  dma-names:
    const: rx

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the input port.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false
            description: Endpoint connected to input device

            properties:
              bus-type:
                enum: [4, 5, 6]
                default: 4

              bus-width:
                enum: [8, 9, 10, 11, 12, 13, 14]
                default: 14

              clock-noncontinuous:
                type: boolean
                description:
                  Presence of this boolean property decides whether clock is
                  continuous or noncontinuous.

              remote-endpoint: true

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Output port node, single endpoint describing the output port.

        properties:
          endpoint:
            unevaluatedProperties: false
            $ref: video-interfaces.yaml#
            description: Endpoint connected to output device

            properties:
              bus-type:
                enum: [5, 6]
                default: 5

              bus-width:
                enum: [8, 9, 10, 11, 12, 13, 14]
                default: 14

              remote-endpoint: true

    required:
      - port@0
      - port@1

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - ports

examples:
  # Example for connecting to a parallel sensor controller block (video pipe)
  # and the input is received from Synopsys IDI interface
  - |
    csi2dc@e1404000 {
        compatible = "microchip,sama7g5-csi2dc";
        reg = <0xe1404000 0x500>;
        clocks = <&pclk>, <&scck>;
        clock-names = "pclk", "scck";

        ports {
               #address-cells = <1>;
               #size-cells = <0>;
               port@0 {
                       reg = <0>; /* must be 0, first child port */
                       csi2dc_in: endpoint { /* input from IDI interface */
                               bus-type = <4>; /* MIPI CSI2 D-PHY */
                               remote-endpoint = <&csi2host_out>;
                       };
               };

               port@1 {
                       reg = <1>; /* must be 1, second child port */
                       csi2dc_out: endpoint {
                               remote-endpoint = <&xisc_in>; /* output to sensor controller */
                       };
               };
        };
    };

  # Example for connecting to a DMA master as an AHB slave
  # and the input is received from Synopsys IDI interface
  - |
    #include <dt-bindings/dma/at91.h>
    csi2dc@e1404000 {
        compatible = "microchip,sama7g5-csi2dc";
        reg = <0xe1404000 0x500>;
        clocks = <&pclk>, <&scck>;
        clock-names = "pclk", "scck";
        dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>;
        dma-names = "rx";

        ports {
               #address-cells = <1>;
               #size-cells = <0>;
               port@0 {
                       reg = <0>; /* must be 0, first child port */
                       csi2dc_input: endpoint { /* input from IDI interface */
                               remote-endpoint = <&csi2host_out>;
                       };
               };

               port@1 {
                       reg = <1>;
               };
        };
    };

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