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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / iommu / renesas,ipmmu-vmsa.yaml
blob: be90f68c11d18b03c748d2cbb1e8be18fb9294aa [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13 The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14 It provides address translation for bus masters outside of the CPU, each
15 connected to the IPMMU through a port called micro-TLB.
16
17properties:
18 compatible:
19 oneOf:
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
23 - renesas,ipmmu-r8a7742 # RZ/G1H
24 - renesas,ipmmu-r8a7743 # RZ/G1M
25 - renesas,ipmmu-r8a7744 # RZ/G1N
26 - renesas,ipmmu-r8a7745 # RZ/G1E
27 - renesas,ipmmu-r8a7790 # R-Car H2
28 - renesas,ipmmu-r8a7791 # R-Car M2-W
29 - renesas,ipmmu-r8a7793 # R-Car M2-N
30 - renesas,ipmmu-r8a7794 # R-Car E2
31 - const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32
33 - items:
34 - enum:
35 - renesas,ipmmu-r8a774a1 # RZ/G2M
36 - renesas,ipmmu-r8a774b1 # RZ/G2N
37 - renesas,ipmmu-r8a774c0 # RZ/G2E
38 - renesas,ipmmu-r8a774e1 # RZ/G2H
39 - renesas,ipmmu-r8a7795 # R-Car H3
40 - renesas,ipmmu-r8a7796 # R-Car M3-W
41 - renesas,ipmmu-r8a77961 # R-Car M3-W+
42 - renesas,ipmmu-r8a77965 # R-Car M3-N
43 - renesas,ipmmu-r8a77970 # R-Car V3M
44 - renesas,ipmmu-r8a77980 # R-Car V3H
45 - renesas,ipmmu-r8a77990 # R-Car E3
46 - renesas,ipmmu-r8a77995 # R-Car D3
47
48 - items:
49 - enum:
50 - renesas,ipmmu-r8a779a0 # R-Car V3U
51 - renesas,ipmmu-r8a779f0 # R-Car S4-8
52 - renesas,ipmmu-r8a779g0 # R-Car V4H
53 - const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4
54
55 reg:
56 maxItems: 1
57
58 interrupts:
59 minItems: 1
60 description:
61 Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
62 items:
63 - description: non-secure mode
64 - description: secure mode if supported
65
66 '#iommu-cells':
67 const: 1
68 description:
69 The number of the micro-TLB that the device is connected to.
70
71 power-domains:
72 maxItems: 1
73
74 renesas,ipmmu-main:
75 $ref: /schemas/types.yaml#/definitions/phandle-array
76 items:
77 - minItems: 1
78 items:
79 - description: phandle to main IPMMU
80 - description:
81 The interrupt bit number associated with the particular cache
82 IPMMU device. If present, the interrupt bit number needs to match
83 the main IPMMU IMSSTR register. Only used by cache IPMMU
84 instances.
85 description:
86 Reference to the main IPMMU.
87
88required:
89 - compatible
90 - reg
91 - '#iommu-cells'
92
93oneOf:
94 - required:
95 - interrupts
96 - required:
97 - renesas,ipmmu-main
98
99additionalProperties: false
100
101allOf:
102 - if:
103 properties:
104 compatible:
105 not:
106 contains:
107 const: renesas,ipmmu-vmsa
108 then:
109 required:
110 - power-domains
111
112 - if:
113 properties:
114 compatible:
115 contains:
116 const: renesas,rcar-gen4-ipmmu-vmsa
117 then:
118 properties:
119 renesas,ipmmu-main:
120 items:
121 - maxItems: 1
122 else:
123 properties:
124 renesas,ipmmu-main:
125 items:
126 - minItems: 2
127
128examples:
129 - |
130 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
131 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 #include <dt-bindings/power/r8a7791-sysc.h>
133
134 ipmmu_mx: iommu@fe951000 {
135 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
136 reg = <0xfe951000 0x1000>;
137 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
139 #iommu-cells = <1>;
140 };