| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner D1 General Purpose ADC |
| 8 | |
| 9 | maintainers: |
| 10 | - Maksim Kiselev <bigunclemax@gmail.com> |
| 11 | |
| 12 | properties: |
| 13 | compatible: |
| 14 | enum: |
| 15 | - allwinner,sun20i-d1-gpadc |
| 16 | |
| 17 | "#io-channel-cells": |
| 18 | const: 1 |
| 19 | |
| 20 | "#address-cells": |
| 21 | const: 1 |
| 22 | |
| 23 | "#size-cells": |
| 24 | const: 0 |
| 25 | |
| 26 | clocks: |
| 27 | maxItems: 1 |
| 28 | |
| 29 | interrupts: |
| 30 | maxItems: 1 |
| 31 | |
| 32 | reg: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | resets: |
| 36 | maxItems: 1 |
| 37 | |
| 38 | patternProperties: |
| 39 | "^channel@[0-9a-f]+$": |
| 40 | $ref: adc.yaml |
| 41 | type: object |
| 42 | description: |
| 43 | Represents the internal channels of the ADC. |
| 44 | |
| 45 | properties: |
| 46 | reg: |
| 47 | items: |
| 48 | minimum: 0 |
| 49 | maximum: 15 |
| 50 | |
| 51 | required: |
| 52 | - reg |
| 53 | |
| 54 | unevaluatedProperties: false |
| 55 | |
| 56 | required: |
| 57 | - "#io-channel-cells" |
| 58 | - clocks |
| 59 | - compatible |
| 60 | - interrupts |
| 61 | - reg |
| 62 | - resets |
| 63 | |
| 64 | additionalProperties: false |
| 65 | |
| 66 | examples: |
| 67 | - | |
| 68 | #include <dt-bindings/clock/sun20i-d1-ccu.h> |
| 69 | #include <dt-bindings/reset/sun20i-d1-ccu.h> |
| 70 | #include <dt-bindings/interrupt-controller/irq.h> |
| 71 | |
| 72 | gpadc: adc@2009000 { |
| 73 | compatible = "allwinner,sun20i-d1-gpadc"; |
| 74 | reg = <0x2009000 0x400>; |
| 75 | clocks = <&ccu CLK_BUS_GPADC>; |
| 76 | resets = <&ccu RST_BUS_GPADC>; |
| 77 | interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | #io-channel-cells = <1>; |
| 79 | |
| 80 | #address-cells = <1>; |
| 81 | #size-cells = <0>; |
| 82 | |
| 83 | channel@0 { |
| 84 | reg = <0>; |
| 85 | }; |
| 86 | |
| 87 | channel@1 { |
| 88 | reg = <1>; |
| 89 | }; |
| 90 | }; |
| 91 | ... |