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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car I2C Controller
8
9maintainers:
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11
12properties:
13 compatible:
14 oneOf:
15 - items:
16 - enum:
17 - renesas,i2c-r8a7778 # R-Car M1A
18 - renesas,i2c-r8a7779 # R-Car H1
19 - const: renesas,rcar-gen1-i2c # R-Car Gen1
20
21 - items:
22 - enum:
23 - renesas,i2c-r8a7742 # RZ/G1H
24 - renesas,i2c-r8a7743 # RZ/G1M
25 - renesas,i2c-r8a7744 # RZ/G1N
26 - renesas,i2c-r8a7745 # RZ/G1E
27 - renesas,i2c-r8a77470 # RZ/G1C
28 - renesas,i2c-r8a7790 # R-Car H2
29 - renesas,i2c-r8a7791 # R-Car M2-W
30 - renesas,i2c-r8a7792 # R-Car V2H
31 - renesas,i2c-r8a7793 # R-Car M2-N
32 - renesas,i2c-r8a7794 # R-Car E2
33 - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1
34
35 - items:
36 - enum:
37 - renesas,i2c-r8a774a1 # RZ/G2M
38 - renesas,i2c-r8a774b1 # RZ/G2N
39 - renesas,i2c-r8a774c0 # RZ/G2E
40 - renesas,i2c-r8a774e1 # RZ/G2H
41 - renesas,i2c-r8a7795 # R-Car H3
42 - renesas,i2c-r8a7796 # R-Car M3-W
43 - renesas,i2c-r8a77961 # R-Car M3-W+
44 - renesas,i2c-r8a77965 # R-Car M3-N
45 - renesas,i2c-r8a77970 # R-Car V3M
46 - renesas,i2c-r8a77980 # R-Car V3H
47 - renesas,i2c-r8a77990 # R-Car E3
48 - renesas,i2c-r8a77995 # R-Car D3
49 - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
50
51 - items:
52 - enum:
53 - renesas,i2c-r8a779a0 # R-Car V3U
54 - renesas,i2c-r8a779f0 # R-Car S4-8
55 - renesas,i2c-r8a779g0 # R-Car V4H
56 - const: renesas,rcar-gen4-i2c # R-Car Gen4
57
58 reg:
59 maxItems: 1
60
61 interrupts:
62 maxItems: 1
63
64 clock-frequency:
65 description:
66 Desired I2C bus clock frequency in Hz. The absence of this property
67 indicates the default frequency 100 kHz.
68
69 clocks:
70 maxItems: 1
71
72 power-domains:
73 maxItems: 1
74
75 resets:
76 maxItems: 1
77
78 dmas:
79 minItems: 2
80 maxItems: 4
81 description:
82 Must contain a list of pairs of references to DMA specifiers, one for
83 transmission, and one for reception.
84
85 dma-names:
86 minItems: 2
87 maxItems: 4
88 items:
89 enum:
90 - tx
91 - rx
92
93 i2c-scl-falling-time-ns:
94 default: 35
95 description:
96 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
97 specification.
98
99 i2c-scl-internal-delay-ns:
100 default: 50
101 description:
102 Number of nanoseconds the IP core additionally needs to setup SCL.
103
104 i2c-scl-rising-time-ns:
105 default: 200
106 description:
107 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
108 specification.
109
110required:
111 - compatible
112 - reg
113 - interrupts
114 - clocks
115 - power-domains
116 - '#address-cells'
117 - '#size-cells'
118
119allOf:
120 - $ref: /schemas/i2c/i2c-controller.yaml#
121
122 - if:
123 properties:
124 compatible:
125 contains:
126 enum:
127 - renesas,rcar-gen1-i2c
128 - renesas,rcar-gen2-i2c
129 then:
130 properties:
131 dmas: false
132 dma-names: false
133
134 - if:
135 properties:
136 compatible:
137 contains:
138 enum:
139 - renesas,rcar-gen2-i2c
140 - renesas,rcar-gen3-i2c
141 - renesas,rcar-gen4-i2c
142 then:
143 required:
144 - resets
145
146unevaluatedProperties: false
147
148examples:
149 - |
150 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
151 #include <dt-bindings/interrupt-controller/arm-gic.h>
152 #include <dt-bindings/power/r8a7791-sysc.h>
153
154 i2c0: i2c@e6508000 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
158 reg = <0xe6508000 0x40>;
159 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
160 clock-frequency = <400000>;
161 clocks = <&cpg CPG_MOD 931>;
162 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
163 resets = <&cpg 931>;
164 i2c-scl-internal-delay-ns = <6>;
165 };