| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : Should be "fsl,<soc>-gpio" |
| 5 | The following <soc>s are known to be supported: |
| 6 | mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq, |
| 7 | ls1021a, ls1043a, ls2080a, ls1028a, ls1088a. |
| 8 | - reg : Address and length of the register set for the device |
| 9 | - interrupts : Should be the port interrupt shared by all 32 pins. |
| 10 | - #gpio-cells : Should be two. The first cell is the pin number and |
| 11 | the second cell is used to specify the gpio polarity: |
| 12 | 0 = active high |
| 13 | 1 = active low |
| 14 | |
| 15 | Optional properties: |
| 16 | - little-endian : GPIO registers are used as little endian. If not |
| 17 | present registers are used as big endian by default. |
| 18 | |
| 19 | Example of gpio-controller node for a mpc5125 SoC: |
| 20 | |
| 21 | gpio0: gpio@1100 { |
| 22 | compatible = "fsl,mpc5125-gpio"; |
| 23 | #gpio-cells = <2>; |
| 24 | reg = <0x1100 0x080>; |
| 25 | interrupts = <78 0x8>; |
| 26 | }; |
| 27 | |
| 28 | Example of gpio-controller node for a ls2080a SoC: |
| 29 | |
| 30 | gpio0: gpio@2300000 { |
| 31 | compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; |
| 32 | reg = <0x0 0x2300000 0x0 0x10000>; |
| 33 | interrupts = <0 36 0x4>; /* Level high type */ |
| 34 | gpio-controller; |
| 35 | little-endian; |
| 36 | #gpio-cells = <2>; |
| 37 | interrupt-controller; |
| 38 | #interrupt-cells = <2>; |
| 39 | }; |
| 40 | |
| 41 | |
| 42 | Example of gpio-controller node for a ls1028a/ls1088a SoC: |
| 43 | |
| 44 | gpio1: gpio@2300000 { |
| 45 | compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; |
| 46 | reg = <0x0 0x2300000 0x0 0x10000>; |
| 47 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | gpio-controller; |
| 49 | #gpio-cells = <2>; |
| 50 | interrupt-controller; |
| 51 | #interrupt-cells = <2>; |
| 52 | little-endian; |
| 53 | }; |