| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: NVIDIA Tegra HDMI Output Encoder |
| 8 | |
| 9 | maintainers: |
| 10 | - Thierry Reding <thierry.reding@gmail.com> |
| 11 | - Jon Hunter <jonathanh@nvidia.com> |
| 12 | |
| 13 | properties: |
| 14 | $nodename: |
| 15 | pattern: "^hdmi@[0-9a-f]+$" |
| 16 | |
| 17 | compatible: |
| 18 | oneOf: |
| 19 | - enum: |
| 20 | - nvidia,tegra20-hdmi |
| 21 | - nvidia,tegra30-hdmi |
| 22 | - nvidia,tegra114-hdmi |
| 23 | - nvidia,tegra124-hdmi |
| 24 | |
| 25 | - items: |
| 26 | - const: nvidia,tegra132-hdmi |
| 27 | - const: nvidia,tegra124-hdmi |
| 28 | |
| 29 | reg: |
| 30 | maxItems: 1 |
| 31 | |
| 32 | interrupts: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | clocks: |
| 36 | items: |
| 37 | - description: module clock |
| 38 | - description: parent clock |
| 39 | |
| 40 | clock-names: |
| 41 | items: |
| 42 | - const: hdmi |
| 43 | - const: parent |
| 44 | |
| 45 | resets: |
| 46 | items: |
| 47 | - description: module reset |
| 48 | |
| 49 | reset-names: |
| 50 | items: |
| 51 | - const: hdmi |
| 52 | |
| 53 | operating-points-v2: true |
| 54 | |
| 55 | power-domains: |
| 56 | items: |
| 57 | - description: phandle to the core power domain |
| 58 | |
| 59 | hdmi-supply: |
| 60 | description: supply for the +5V HDMI connector pin |
| 61 | |
| 62 | vdd-supply: |
| 63 | description: regulator for supply voltage |
| 64 | |
| 65 | pll-supply: |
| 66 | description: regulator for PLL |
| 67 | |
| 68 | nvidia,ddc-i2c-bus: |
| 69 | description: phandle of an I2C controller used for DDC EDID |
| 70 | probing |
| 71 | $ref: /schemas/types.yaml#/definitions/phandle |
| 72 | |
| 73 | nvidia,hpd-gpio: |
| 74 | description: specifies a GPIO used for hotplug detection |
| 75 | maxItems: 1 |
| 76 | |
| 77 | nvidia,edid: |
| 78 | description: supplies a binary EDID blob |
| 79 | $ref: /schemas/types.yaml#/definitions/uint8-array |
| 80 | |
| 81 | nvidia,panel: |
| 82 | description: phandle of a display panel |
| 83 | $ref: /schemas/types.yaml#/definitions/phandle |
| 84 | |
| 85 | "#sound-dai-cells": |
| 86 | const: 0 |
| 87 | |
| 88 | additionalProperties: false |
| 89 | |
| 90 | required: |
| 91 | - compatible |
| 92 | - reg |
| 93 | - interrupts |
| 94 | - clocks |
| 95 | - clock-names |
| 96 | - resets |
| 97 | - reset-names |
| 98 | - pll-supply |
| 99 | - vdd-supply |
| 100 | - nvidia,ddc-i2c-bus |
| 101 | - nvidia,hpd-gpio |
| 102 | |
| 103 | examples: |
| 104 | - | |
| 105 | #include <dt-bindings/clock/tegra124-car.h> |
| 106 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 107 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 108 | |
| 109 | hdmi@54280000 { |
| 110 | compatible = "nvidia,tegra124-hdmi"; |
| 111 | reg = <0x54280000 0x00040000>; |
| 112 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, |
| 114 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; |
| 115 | clock-names = "hdmi", "parent"; |
| 116 | resets = <&tegra_car 51>; |
| 117 | reset-names = "hdmi"; |
| 118 | |
| 119 | hdmi-supply = <&vdd_5v0_hdmi>; |
| 120 | pll-supply = <&vdd_hdmi_pll>; |
| 121 | vdd-supply = <&vdd_3v3_hdmi>; |
| 122 | |
| 123 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 124 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| 125 | }; |