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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Functional Clock Controller for MT8188
8
9maintainers:
10 - Garmin Chang <garmin.chang@mediatek.com>
11
12description: |
13 The clock architecture in MediaTek like below
14 PLLs -->
15 dividers -->
16 muxes
17 -->
18 clock gate
19
20 The devices provide clock gate control in different IP blocks.
21
22properties:
23 compatible:
24 enum:
25 - mediatek,mt8188-adsp-audio26m
26 - mediatek,mt8188-camsys
27 - mediatek,mt8188-camsys-rawa
28 - mediatek,mt8188-camsys-rawb
29 - mediatek,mt8188-camsys-yuva
30 - mediatek,mt8188-camsys-yuvb
31 - mediatek,mt8188-ccusys
32 - mediatek,mt8188-imgsys
33 - mediatek,mt8188-imgsys-wpe1
34 - mediatek,mt8188-imgsys-wpe2
35 - mediatek,mt8188-imgsys-wpe3
36 - mediatek,mt8188-imgsys1-dip-nr
37 - mediatek,mt8188-imgsys1-dip-top
38 - mediatek,mt8188-imp-iic-wrap-c
39 - mediatek,mt8188-imp-iic-wrap-en
40 - mediatek,mt8188-imp-iic-wrap-w
41 - mediatek,mt8188-ipesys
42 - mediatek,mt8188-mfgcfg
43 - mediatek,mt8188-vdecsys
44 - mediatek,mt8188-vdecsys-soc
45 - mediatek,mt8188-vencsys
46 - mediatek,mt8188-vppsys0
47 - mediatek,mt8188-vppsys1
48 - mediatek,mt8188-wpesys
49 - mediatek,mt8188-wpesys-vpp0
50
51 reg:
52 maxItems: 1
53
54 '#clock-cells':
55 const: 1
56
57required:
58 - compatible
59 - reg
60 - '#clock-cells'
61
62additionalProperties: false
63
64examples:
65 - |
66 clock-controller@11283000 {
67 compatible = "mediatek,mt8188-imp-iic-wrap-c";
68 reg = <0x11283000 0x1000>;
69 #clock-cells = <1>;
70 };
71