Bindings/clock/calxeda.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/calxeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda highbank platform Clock Controller

description: |
  This binding covers the Calxeda SoC internal peripheral and bus clocks
  as used by peripherals. The clocks live inside the "system register"
  region of the SoC, so are typically presented as children of an
  "hb-sregs" node.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  "#clock-cells":
    const: 0

  compatible:
    enum:
      - calxeda,hb-pll-clock
      - calxeda,hb-a9periph-clock
      - calxeda,hb-a9bus-clock
      - calxeda,hb-emmc-clock

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - "#clock-cells"
  - compatible
  - clocks
  - reg

additionalProperties: false

examples:
  - |
    sregs@3fffc000 {
        compatible = "calxeda,hb-sregs";
        reg = <0x3fffc000 0x1000>;

        clocks {
            #address-cells = <1>;
            #size-cells = <0>;

            osc: oscillator {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <33333000>;
            };

            ddrpll: ddrpll@108 {
                #clock-cells = <0>;
                compatible = "calxeda,hb-pll-clock";
                clocks = <&osc>;
                reg = <0x108>;
            };

            a9pll: a9pll@100 {
                #clock-cells = <0>;
                compatible = "calxeda,hb-pll-clock";
                clocks = <&osc>;
                reg = <0x100>;
            };

            a9periphclk: a9periphclk@104 {
                #clock-cells = <0>;
                compatible = "calxeda,hb-a9periph-clock";
                clocks = <&a9pll>;
                reg = <0x104>;
            };
        };
    };

...